Variable width memory module supporting enhanced error detection and correction
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
1. A data buffer component comprising:
a primary data port to couple to a memory-controller component;
first and second secondary data ports to couple to respective first and second memory components; and
multiplexing circuitry supporting a first access mode and a time-division-multiplexing mode, wherein:
in the first access mode, the multiplexing circuitry communicates, to the primary data port, first data bursts from the first secondary data port separate from second data bursts from the second secondary data port; and
in the time-division-multiplexing mode, the multiplexing circuitry communicates, to the primary data port, ones of the first data bursts from the first secondary data port interleaved with ones of the second data bursts from the second secondary data port.
2. The data buffer of claim 1 , further comprising a buffer control interface to receive buffer commands, each command directing the data buffer to communicate one of the first and second data bursts in the first access mode and one of the first data bursts interleaved with one of the second data bursts in the time-division-multiplexing mode.
3. The data buffer of claim 1 , further comprising a second primary data port to couple to the memory-controller component and third and fourth secondary data ports to couple to respective third and fourth memory components.
4. The data buffer of claim 3 , the multiplexing circuitry supporting a second access mode to communicate third data bursts from the third secondary data port and fourth data bursts from the fourth secondary data port to the first-mentioned primary data port and the second primary data port.
5. The data buffer of claim 4 , the multiplexing circuitry supporting a second time-division-multiplexing mode in which the multiplexing circuitry communicates, to the second primary data port, ones of the third data bursts from the third secondary data port interleaved with ones of the fourth data bursts from the fourth secondary data port.
6. The data buffer of claim 3 , wherein the multiplexing circuitry is configurable to relay signals between the first-mentioned primary data port and the second primary data port.
7. The data buffer of claim 1 , wherein the multiplexing circuitry communicates the first data bursts from the first secondary port and the second data bursts from the secondary data port at a first bit rate, and communicates the interleaved first and second data bursts from the primary data port at a second bit rate higher than the first bit rate.
8. The data buffer of claim 7 , wherein the first bit rate is half the second bit rate.
9. A method of communicating data between first and second memory components and a memory-controller component, the method comprising:
in a first access mode, communicating first data bursts from the first memory component to the memory-controller component separate from second data bursts from the second memory component to the memory-controller component; and
in a time-division-multiplexing mode, communicating ones of the first data bursts from the first memory component to the memory-controller component interleaved with ones of the second data bursts from the second memory component.
10. The method of claim 9 , further comprising communicating a single data burst of the first and second data bursts responsive to a single read command in the first access mode.
11. The method of claim 10 , further comprising communicating one of the first data bursts interleaved with one of the second data bursts responsive to the single read command in the time-division-multiplexing mode.
12. The method of claim 9 , further comprising communicating the first data bursts and the second data bursts at a first bit rate in the first access mode and communicating the ones of the first data bursts interleaved with the ones of the second data bursts at a second bit rate greater than the first bit rate.
13. The method of claim 12 , wherein the first bit rate is half the second bit rate.
14. The method of claim 9 , further comprising, in the time-division-multiplexing mode, combining the ones of the first data bursts and the ones of the second data bursts for error detection.
15. The method of claim 9 , wherein the time-division-multiplexing mode conveys the ones of the first data bursts interleaved with ones of the second data bursts at a first data width, the method further comprising a second time-division-multiplexing mode to convey the ones of the first data bursts interleaved with ones of the second data bursts at a second data width greater than the first data width.
16. A data buffer component comprising:
a primary data port to couple to a memory-controller component;
first and second secondary data ports to couple to respective first and second memory components; and
means for supporting a first access mode and a time-division-multiplexing mode, wherein:
in the first access mode, communicating to the primary data port first data bursts from the first secondary data port separate from second data bursts from the second secondary data port; and
in the time-division-multiplexing mode, communicating to the primary data port ones of the first data bursts from the first secondary data port interleaved with ones of the second data bursts from the second secondary data port.
17. The data buffer of claim 16 , the means for supporting the first access mode and the time-division-multiplexing mode communicating one of the first and second data bursts responsive to a single command in the first access mode and communicating the one of the first data bursts interleaved with one of the second data bursts responsive to the single command in the time-division-multiplexing mode.
18. The data buffer of claim 16 , the means for supporting the first access mode and the time-division-multiplexing mode communicating the first data bursts and the second data bursts at a first bit rate in the first access mode and communicating the ones of the first data bursts interleaved with the ones of the second data bursts at a second bit rate greater than the first bit rate.
19. The data buffer of claim 18 , wherein the first bit rate is half the second bit rate.