Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering
Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
1. An apparatus comprising:
a first structure comprising metal;
a second structure comprising metal;
a third structure comprising ferroelectric or anti-ferroelectric material, wherein the third structure is between and adjacent to the first and second structures;
a fourth structure adjacent to the first structure, wherein the fourth structure is to provide tensile stress to the ferroelectric or anti-ferroelectric material, wherein the fourth structure comprises metal, semimetal, or oxide, and wherein the fourth structure has a thickness in a range of 5 A to 200 A;
a first barrier structure adjacent to the first structure; and
a second barrier structure adjacent to the first structure, wherein the first and second barrier structures comprise Ta and N.
2. The apparatus of claim 1 , wherein the ferroelectric material is a super lattice of a first material and a second material, wherein the first material includes one of: PbTiO 3 (PTO), SrZrO 3 , or FeO3, and wherein the second material includes one of: SrTiO 3 (STO), BaZrO 3 , or YTiO 3 .
3. The apparatus of claim 1 , wherein the ferroelectric material includes one or more of: Hf or Zr, and wherein the ferroelectric material has polar orthorhombic phase or wherein the anti-ferroelectric material has tetragonal phase.
4. The apparatus of claim 1 , wherein the ferroelectric material includes one or more of: Pb, Ti, Zr, Ba, N Si, La, Al, or Hf; and wherein the ferroelectric material has polar orthorhombic phase.
5. The apparatus of claim 1 , wherein the fourth structure includes an oxide of one or more of: Al, Ti, Hf, Si, Jr, or N.
6. The apparatus of claim 1 , wherein the ferroelectric material has a thickness in a range of 2 nm to 30 nm.
7. An apparatus comprising:
a bit-line;
a word-line;
a transistor coupled to the bit-line and the word-line; and
a capacitor over the bit-line (COB), wherein the COB is coupled to ground and the transistor, wherein the COB comprises:
a first structure comprising metal;
a second structure comprising metal;
a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures;
a fourth structure adjacent to the first structure, wherein the fourth structure is to provide tensile stress to the ferroelectric material, wherein the fourth structure comprises metal, semimetal, or oxide, and wherein the fourth structure has a thickness in a range of 5 A to 200 A;
a first barrier structure adjacent to the first structure; and
a second barrier structure adjacent to the first structure, wherein the first and second barrier structures comprise Ta and N.
8. The apparatus of claim 7 , wherein the ferroelectric material includes one or more of: Hf or Zr; and wherein the ferroelectric material has polar orthorhombic phase.
9. The apparatus of claim 7 , wherein the fourth structure includes an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N.
10. The apparatus of claim 7 comprising a first interconnect adjacent to the first barrier; and a second interconnect adjacent to the second barrier.
11. The apparatus of claim 10 , wherein the first and second interconnect comprise metal including one or more of: Cu, Al, graphene, carbon nanotube, Ay, Co, or Ti.