Systems and methods for estimating wire capacitance in a register-transfer level circuit design
Example systems and methods are disclosed for estimating wire capacitance in an RTL circuit design. In an embodiment, a reference post-layout design is received from a non-transitory storage medium, and gate-level nets within the reference post-layout design are classified as either long nets or short nets based, at least in part, on an average fanout length within the gate-level net. A parasitic model may be generated for each of the gate-level nets, and the gate-level nets and associated parasitic models may be stored within either a long net database or a short net database based on the classification of the gate-level net. A net from the RTL circuit design may be classified as either long or short based, at least in part, on a number of modules crossed by one or more fanouts within the net. If the net from the RTL circuit design is classified as long, then capacitance for the net may be estimated using a parasitic model selected from the long net database. If the net from the RTL circuit design is classified as short, then capacitance for the net may be estimated using a parasitic model selected from the short net database.
1. A method for estimating capacitance of a net in a register-transfer level (RTL) circuit design, comprising:
determining, by a processor, an average fanout length for each respective gate-level net within a reference post-layout design for the RTL circuit design, wherein the average fanout length is determined based on coordinate information identifying source and sink pins for the respective gate-level nets within the reference post-layout design;
determining, by the processor, an overall average fanout length and a standard deviation for the gate-level nets within the reference post-layout design
classifying, by the processor, a gate-level net within the reference post-layout design based on a difference between an average fanout length for the gate-level net and the overall average fanout length with the standard deviation;
generating, by the processor, a parasitic model for the gate-level net, the parasitic model identifying a total wire capacitance;
storing the model in a database according to the classification of the gate-level net;
classifying, by the processor, a net from the RTL circuit design based on a number of modules crossed by one or more fanouts within the net from the RTL circuit design; and
selecting the parasitic model in the database to estimate capacitance for the net from the RTL circuit design, wherein the parasitic model in the database is selected based on the classification of the gate-level net and the classification of the net from the RTL circuit design.
2. The method of claim 1 , wherein the parasitic model for the gate-level net further identifies a total square deviation of wire capacitance within the gate-level net.
3. The method of claim 1 , wherein the parasitic model for the gate-level net further identifies a total number of nets within the RTL circuit design.
4. The method of claim 1 , wherein the gate-level net is further classified within the database based on a total number of fanouts and a net function.
5. The method of claim 4 , further comprising:
further classifying the net from the RTL circuit design based on a total number of fanouts and a net function;
wherein the further classification is used in selecting the parasitic model from the database.
6. The method of claim 1 , wherein classifying the net from the RTL circuit design further comprises:
sorting a plurality of nets from the RTL circuit design based on an indicator of wire length within each of the plurality of nets;
determining a ratio of long to short nets stored within the database; and
classifying the sorted plurality of nets as either long or short to maintain the ratio of long to short nets.
7. The method of claim 1 , wherein the database comprises a long net database configured to store long net parasitic models and a short net database configured to store short net parasitic models.
8. A system for estimating capacitance of a net in a register-transfer level (RTL) circuit design, comprising:
one or more non-transitory storage medium storing a reference post-layout design for the RTL circuit design;
RTL power estimation software stored on the one or more non-transitory storage medium and executable by one or more processors, the RTL power estimation software when executed being configured to,
determine an average fanout length for each respective gate-level net within the reference post-layout design, wherein the average fanout length is determined based on coordinate information identifying source and sink pins for the respective gate-level nets within the reference post-layout design;
determine an overall average fanout length and a standard deviation for the gate-level nets within the reference post-layout design
classify a gate-level net within the reference post-layout design based on a difference between an average fanout length for the gate-level net and the overall average fanout length with the standard deviation,
generate a parasitic model for the gate-level net, the parasitic model identifying a total wire capacitance;
store the parasitic model in a database according to the classification of the gate-level net,
classify a net from the RTL circuit design based on a number of modules crossed by one or more fanouts within the net from the RTL circuit design, and
select the parasitic model in the database to estimate capacitance for the net from the RTL circuit design, wherein the parasitic model in the database is selected based on the classification of the gate-level net and the classification of the net form the RTL circuit design.
9. The system of claim 8 , wherein the parasitic model for the gate-level net further identifies a total square deviation of wire capacitance within the gate-level net.
10. The system of claim 8 , wherein the parasitic model for the gate-level net further identifies a total number of nets within the RTL circuit design.
11. The system claim 8 , wherein the gate-level net is further classified based on a total number of fanouts and a net function.
12. The system of claim 11 , wherein the RTL power estimation software is further configured to:
further classify the net from the RTL circuit design based on a total number of fanouts and a net function,
wherein the further classification is used in selecting the parasitic model.
13. The system of claim 8 , wherein classifying the net from the RTL circuit design further comprises:
sorting a plurality of nets from the RTL circuit design based on an indicator of wire length within each of the plurality of nets;
determining a ratio of long to short nets stored within the database;
classifying the sorted plurality of nets as either long or short to maintain the ratio of long to short nets.
14. A non-transitory computer-readable storage medium comprising instructions for which when executed cause a processing system to execute steps comprising:
determining, by the processor, an average fanout length for each respective gate-level net within a reference post-layout design for the RTL circuit design, wherein the average fanout length is determined based on coordinate information identifying source and sink pins for the respective gate-level nets within the reference post-layout design;
determining, by the processor, an overall average fanout length and a standard deviation for the gate-level nets within the reference post-layout design
classifying, by the processor, a gate-level net within the reference post-layout design based on a difference between an average fanout length for the gate-level net and the overall average fanout length with the standard deviation;
generating, by the processor, a parasitic model for the gate-level net, the parasitic model identifying a total wire capacitance;
storing the parasitic model in a database according to the classification of the gate-level net;
classifying, by the processor, a net from the RTL circuit design based on a number of modules crossed by one or more fanouts within the net from the RTL circuit design; and
selecting the parasitic model in the database to estimate capacitance for the net from the RTL circuit design, wherein the parasitic model in the database is selected based on the classification of the gate-level net and the classification of the net from the RTL circuit design.
15. The non-transitory computer-readable storage medium of claim 14 , wherein the parasitic model for the gate-level net further identifies a total square deviation of wire capacitance within the gate-level net.
16. The non-transitory computer-readable storage medium of claim 14 , wherein the parasitic model for the gate-level net further identifies a total number of nets within the RTL circuit design.
17. The non-transitory computer-readable storage medium of claim 14 , wherein classifying the net from the RTL circuit design as further comprises:
sorting a plurality of nets from the RTL circuit design based on an indicator of wire length within each of the plurality of nets;
determining a ratio of long to short nets stored within the database; and
classifying the sorted plurality of nets as either long or short to maintain the ratio of long to short nets.