Semiconductor package including cavity-mounted device

1. A package comprising:

a substrate;

a first die disposed within the substrate, wherein a back surface of the first die is attached to the substrate by a first adhesive;

a first underfill material between the first die and the substrate, the first underfill material extending along a first sidewall of the first adhesive and a second sidewall of the first die from the back surface of the first die to a front surface of the first die, wherein at least a portion of the first sidewall is aligned with at least a portion of the second sidewall;

a redistribution structure over the substrate and the first die;

an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device;

a plurality of conductive connectors bonding the encapsulated device to the redistribution structure; and

a second underfill material extending between the redistribution structure and the encapsulated device, the second underfill material surrounding the plurality of conductive connectors, the second underfill material comprising a material different from an encapsulant encapsulating the encapsulated device.

2. The package of claim 1 , wherein the first die comprises a multilayer ceramic capacitor (MLCC).

3. The package of claim 1 , wherein the first die comprises an integrated passive device (IPD).

4. The package of claim 1 , wherein the first die comprises an integrated voltage regulator (IVR).

5. The package of claim 1 , wherein the first die comprises a static random access memory (SRAM) die.

6. The package of claim 1 , wherein a distance between the encapsulated device and the first die is less than 0.3 mm.

7. The package of claim 1 , wherein the redistribution structure comprises one or more molding compound layers.

8. The package of claim 7 , wherein each of the one or more molding compound layers has a thickness from 5 μm to 100 μm.

9. The package of claim 1 , further comprising a ring structure attached to the redistribution structure, the ring structure surrounding the encapsulated device.

10. The package of claim 1 , further comprising a third underfill material surrounding sidewalls of the first die.

11. A semiconductor package comprising:

a substrate;

a first die attached to the substrate by an adhesive, wherein the first die is disposed within the substrate between a first sidewall of the substrate and a second sidewall of the substrate;

a redistribution structure over the substrate and the first die, the redistribution structure having a width equal to a width of the substrate, the redistribution structure comprising a dielectric layer and a molding compound layer, the molding compound layer comprising a first material different from a second material of the dielectric layer;

a first semiconductor device attached to the redistribution structure and electrically coupled to the redistribution structure;

a second semiconductor device attached to the redistribution structure adjacent the first semiconductor device in a direction parallel to a major surface of the substrate and electrically coupled to the redistribution structure; and

an encapsulant surrounding the first semiconductor device and the second semiconductor device, wherein a top surface of the first semiconductor device opposite the substrate, a top surface of the second semiconductor device opposite the substrate, and a top surface of the encapsulant opposite the substrate are level with one another.

12. The semiconductor package of claim 11 , further comprising an underfill surrounding the first die and the adhesive, the underfill comprising a vertical surface perpendicular to the major surface of the substrate, the vertical surface contacting sidewalls of the first die and the adhesive.

13. The semiconductor package of claim 11 , further comprising a ring structure encircling the first semiconductor device and the second semiconductor device in a plane parallel to the major surface of the substrate, wherein the ring structure is attached to the redistribution structure by a second adhesive.

14. The semiconductor package of claim 11 , wherein the first material of the molding compound layer has a lower impedance than the second material of the dielectric layer.

15. A semiconductor package comprising:

a first device attached to a substrate, wherein the first device is disposed in a cavity in the substrate, the cavity comprising opposite sidewalls and a mounting surface extending between the opposite sidewalls, wherein the first device is attached to the mounting surface, and wherein the first device is disposed between the opposite sidewalls;

a first dielectric layer over the substrate, the first dielectric layer comprising an opening having a first width equal to a second width of the cavity;

an underfill surrounding the first device, the underfill comprising a concave top surface opposite the mounting surface of the substrate, the concave top surface extending from a side surface of the first dielectric layer to a side surface of the first device;

a second device electrically coupled to the first device, the second device being disposed over the first device in a direction perpendicular to a major surface of the substrate; and

an encapsulant surrounding the second device.

16. The semiconductor package of claim 15 , further comprising a front-side redistribution structure over a front-side of the substrate, the first dielectric layer, and the first device, the front-side redistribution structure comprising one or more molding compound layers, wherein the second device is coupled to the first device through the front-side redistribution structure.

17. The semiconductor package of claim 16 , further comprising a conductive plug extending through the substrate from the front-side of the substrate to a backside of the substrate.

18. The semiconductor package of claim 17 , further comprising an electrical connector over a backside of the substrate, wherein the electrical connector is electrically coupled to the front-side redistribution structure through the conductive plug.

19. The semiconductor package of claim 15 , wherein the first device is attached to the substrate by an adhesive.

20. The semiconductor package of claim 15 , further comprising a second dielectric layer over the first dielectric layer, the second dielectric layer contacting a top surface of the first dielectric layer and the concave top surface of the underfill.