Trench capacitor with extended dielectric layer
An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.
1. An integrated circuit structure, comprising:
an interlayer dielectric (ILD) structure comprising dielectric material;
a capacitor within the ILD structure, such that the capacitor is laterally between first and second portions of the ILD structure, the capacitor including first conductive layer on sidewalls of the ILD structure, such that the first conductive layer is laterally between the first and second portions of the ILD structure;
a capacitor dielectric layer on the first conductive layer, such that the capacitor dielectric layer is laterally between first and second portions of the first conductive layer, and wherein the capacitor dielectric layer also laterally extends along a top surface of the ILD structure, the capacitor dielectric layer having an uppermost surface;
a second conductive layer on the capacitor dielectric layer, such that the second conductive layer is laterally between first and second portions of the capacitor dielectric layer, the second conductive layer having an uppermost surface at a same level as the uppermost surface of the capacitor dielectric layer; and
a conductive fill material on the second conductive layer, wherein the conductive fill material is laterally between first and second portions of the second conductive layer.
2. The integrated circuit structure of claim 1 , wherein the ILD structure is an upper ILD structure that is on a lower ILD structure, the lower ILD structure having a conductive feature extending through at least a portion of a thickness of the lower ILD structure, and wherein the first conductive layer contacts the conductive feature.
3. The integrated circuit structure of claim 2 , wherein the conductive feature comprises one of a source contact, a drain contact, a gate contact, a gate electrode, a via, a line, or a contact pad.
4. The integrated circuit structure of claim 2 , wherein the conductive feature is a metal.
5. The integrated circuit structure of claim 1 , wherein the ILD structure is a first ILD structure, the integrated circuit structure further comprising:
a second ILD structure over the first ILD structure, the second ILD structure comprising a dielectric material and a conductive interconnect feature, wherein the conductive interconnect feature contacts at least a portion of the conductive fill material and/or at least a portion of the second conductive layer.
6. The integrated circuit structure of claim 5 , wherein the conductive interconnect feature comprises one of a via or a line.
7. The integrated circuit structure of claim 5 , wherein the conductive interconnect feature is a metal.
8. The integrated circuit structure of claim 5 , wherein the conductive interconnect feature has a laterally extending width that is greater than a laterally extending width of the conductive fill material.
9. The integrated circuit structure of claim 5 , wherein the conductive interconnect feature contacts a portion of the capacitor dielectric layer on the top surface of the first ILD structure.
10. The integrated circuit structure of claim 1 , wherein the capacitor dielectric layer comprises a ferroelectric material.
11. The integrated circuit structure of claim 10 , wherein the ferroelectric material comprises hafnium and at least one of silicon, lanthanum, nitrogen, aluminum, zirconium, germanium, or yttrium.
12. The integrated circuit structure of claim 1 , wherein the second conductive layer extends above the top surface of the ILD structure.
13. An electronic device, comprising:
a chip package comprising one or more semiconductor dies, wherein the one or more semiconductor dies includes at least one capacitor structure, the capacitor structure comprising:
a first conductive layer on sidewalls of an opening through a thickness of a dielectric layer;
a capacitor dielectric layer on the first conductive layer, wherein the capacitor dielectric layer extends above the opening and is on a top surface of the dielectric layer, the capacitor dielectric layer having an uppermost surface;
a second conductive layer on the capacitor dielectric layer, the second conductive layer having an uppermost surface at a same level as the uppermost surface of the capacitor dielectric layer; and
a conductive fill material on the second conductive layer, wherein the conductive fill material fills a remaining portion of the opening.
14. The electronic device of claim 13 , wherein the dielectric layer is on a lower level dielectric layer, the lower level dielectric layer having a metal contact extending through at least a portion of a thickness of the lower level dielectric layer, and wherein the first conductive layer contacts the metal contact.
15. The electronic device of claim 13 , wherein the dielectric layer is a first dielectric layer, the opening is a first opening, and the conductive fill material is a first conductive fill material, the capacitor structure further comprising:
a second dielectric layer over the first dielectric layer; and
a second conductive fill material that fills an opening through a thickness of the second dielectric layer, wherein the second conductive fill material contacts at least a portion of the first conductive fill material.
16. The electronic device of claim 15 , wherein the second conductive fill material has a width that is greater than a width of the first conductive fill material.
17. The electronic device of claim 15 , wherein the second conductive fill material contacts a portion of the capacitor dielectric layer on the top surface of the first dielectric layer.
18. The electronic device of claim 13 , wherein the capacitor dielectric layer comprises a ferroelectric material.
19. The electronic device of claim 18 , wherein the ferroelectric material comprises hafnium and at least one of silicon, lanthanum, nitrogen, aluminum, zirconium, germanium, or yttrium.
20. The electronic device of claim 13 , wherein the second conductive layer extends above the opening.
21. A method of fabricating a capacitor, the method comprising:
depositing a dielectric layer over a substrate;
etching an opening through a thickness of the dielectric layer;
depositing a first conductive layer in the opening and on a top surface of the dielectric layer;
depositing a sacrificial material into the opening such that the sacrificial material fills a remainder of the opening;
removing a portion of the first conductive layer and a portion of the sacrificial material that is above a top surface of the dielectric layer;
removing the sacrificial material from within the opening;
depositing a capacitor dielectric layer in the opening and on a top surface of the dielectric layer;
depositing a second conductive layer in the opening and over a top surface of the dielectric layer;
depositing a conductive fill material into the opening such that the conductive fill material fills a remainder of the opening; and
removing a portion of the second conductive layer and a portion of the conductive fill material that is above the top surface of the dielectric layer to provide the second conductive layer having an uppermost surface at a same level as an uppermost surface of the capacitor dielectric layer.
22. The method of claim 21 , wherein the dielectric layer is a first dielectric layer, the opening is a first opening, and the conductive fill material is a first conductive fill material, the method further comprising:
depositing a second dielectric layer over the first dielectric layer;
etching a second opening through the second dielectric layer such that at least a portion of the first conductive fill material is exposed in the second opening; and
depositing a second conductive fill material in the second opening.
23. The method of claim 22 , wherein etching the second opening comprises etching the second opening having a width that is greater than a width of the first conductive fill material within the opening.
24. The method of claim 22 , wherein etching the second opening comprises exposing a portion of the capacitor dielectric layer on the top surface of the first dielectric layer.
25. The method of claim 21 , wherein removing the portion of the first conductive layer and the portion of the sacrificial material comprises using chemical mechanical polishing (CMP) to remove the portion of the first conductive layer and the portion of the sacrificial material.