Semiconductor device and manufacturing method thereof

1. A method of manufacturing a semiconductor device, comprising:

forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged;

forming a silicide layer over the merged source/drain structures;

forming an interlayer dielectric layer over the merged source/drain structures;

forming a gap in the interlayer dielectric layer in a region between the first and the second transistors; and

separating the first and second transistor structures by etching the merged source/drain structures.

2. The method according to claim 1 , wherein the silicide layer is formed before forming the interlayer dielectric layer.

3. The method according to claim 1 , wherein the silicide layer is formed after the gap is formed.

4. The method according to claim 1 , wherein the gap exposes a portion of the source/drain structures, and the portion of source/drain structures that is exposed is etched during the etching the source/drain structures.

5. The method according to claim 1 , further comprising forming an etch stop layer over the silicide layer.

6. The method according to claim 1 , further comprising forming a photoresist layer over the interlayer dielectric layer.

7. A method of manufacturing a semiconductor device including a plurality of fin field effect transistors (FinFETs), the method comprising:

forming a first fin structure and a second fin structure over a substrate, the first and second fin structures extending in a first direction in plan view,

forming an isolation insulating layer over the substrate so that lower portions of the first and second fin structures are embedded in the isolation insulating layer and upper portions of the first and second fin structures are exposed from the isolation insulating layer;

forming a gate structure over parts of the first and second fin structures, the gate structure including a gate pattern, a dielectric layer disposed between the gate pattern and the first and second fin structures, and a cap insulating layer disposed over the gate pattern, the gate structure extending in a second direction crossing the first direction in plan view;

recessing upper portions of the first and second fin structures,

forming an epitaxial source/drain structure over the recessed first fin structure and the recessed second fin structure,

wherein the epitaxial source/drain structure is a merged structure such that a void is formed between the merged source/drain structure and the isolation insulating layer; and

etching a portion of the merged epitaxial structure between the first and second fin structures to form a first epitaxial source/drain structure and a second epitaxial source/drain structure.

8. The method according to claim 7 , further comprising forming a fin sidewall on sidewalls of the first and second fin structures protruding from the isolation insulating layer and not covered by the gate structure, and on an upper surface of the isolation insulating layer after forming the gate structure,

wherein in the recessing upper portions of the first and second fin structures, a portion of the fin sidewall disposed on the side surfaces of the fin structures is removed and a portion of the fin sidewall disposed on lower side surfaces of the fin structures remains.

9. The method according to claim 7 , wherein in the recessing upper portions of the first and second fin structures, the first and second fin structures are recessed down below the upper surface of the isolation insulating layer.

10. The method according to claim 7 , further comprising, after the first and second epitaxial source/drain structures are formed:

forming a silicide layer on the merged first and second epitaxial source/drain structures;

forming an interlayer dielectric layer; and

forming a gap in the interlayer dielectric layer.

11. The method according to claim 10 , wherein the silicide layer is formed before forming the interlayer dielectric layer.

12. The method according to claim 10 , wherein the silicide layer is formed after the opening is formed.

13. The method according to claim 10 , further comprising forming an etch stop layer over the silicide layer.

14. The method according to claim 7 , further comprising, after the first and second epitaxial source/drain structures are formed:

removing the cap insulating layer, the gate pattern and the dielectric layer so as to make a gate space;

forming a gate dielectric layer in the gate space; and

forming a gate electrode on the gate dielectric layer in the gate space.

15. The method according to claim 14 , wherein the gate dielectric layer is formed of a high-k material.

16. The method according to claim 7 , wherein the first and second source/drain structures comprise a first region comprising SiP having a first P concentration and a second region over the first region having a second P concentration, where the second P concentration is less than the first P concentration.

17. A semiconductor device comprising a plurality of transistors disposed over a common substrate, comprising:

a first transistor comprising a plurality of first fin structures and a second transistor comprising a plurality of second fin structures;

a first merged source/drain structure disposed over the first plurality of fin structures; and

a second merged source drain structure disposed over the second plurality of fin structures,

wherein a pair of adjacent first fin structures are spaced apart by a distance Si and a pair of adjacent second fin structures are spaced apart by the distance S1,

wherein one of the first fin structures is spaced apart from one of the second fin structures adjacent to the one of the first fin structures by a distance S2,

wherein the first merged source/drain structure is spaced apart from the second merged source/drain structure by a distance S3, and

a ratio of S2/S3 ranges from 1.25/1 to 25/1, and

wherein the first and second merged source/drain structures each comprise a first region comprising SiP having a first P concentration and a second region over the first region having a second P concentration, where the second P concentration is less than the first P concentration.

18. The semiconductor device of claim 17 , wherein a ratio S2/S1 ranges from 1.5/1 to 7.5/1.

19. The semiconductor device of claim 17 , wherein S3 ranges from 2 nm to 20 nm.

20. The semiconductor device of claim 17 , wherein S2 ranges from 25 nm to 75 nm.