Methods and apparatus for a track and hold amplifier
Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.
1. A track-and-hold amplifier circuit, comprising:
a gain setting circuit configured to receive an input signal;
a cascode circuit comprising a first terminal, a second terminal, and a third terminal, wherein the cascode circuit is connected to:
the gain setting circuit at a first node via the first terminal, and at a second node via the second terminal; and
a ground node via the third terminal;
a track-and-hold capacitor comprising:
a first capacitor terminal connected to an output node, wherein the output node is selectively connected to the first node; and
a second capacitor terminal; and
an isolation circuit connected to the second capacitor terminal at a third node and the ground node, and wherein the isolation circuit and the cascode circuit share a fourth node.
2. The track-and-hold amplifier circuit according to claim 1 , wherein the isolation circuit is configured to selectively isolate transient current in the track-and-hold capacitor and redirect the transient current through at least a portion of the cascode circuit.
3. The track-and-hold amplifier circuit according to claim 1 , wherein the cascode circuit is:
directly connected to the gain setting circuit at the first node and the second node; and
directly connected to the ground node.
4. The track-and-hold amplifier circuit according to claim 3 , wherein the cascode circuit comprises:
a first transistor directly connected to the first node and a bias voltage; and
a second transistor connected in series with the first transistor and directly connected to the second node.
5. The track-and-hold amplifier circuit according to claim 1 , wherein the track-and-hold amplifier circuit further comprises a first current source directly connected to the first node.
6. The track-and-hold amplifier circuit according to claim 1 , wherein the isolation circuit comprises a clamp device configured to provide a current path from the isolation circuit to the fourth node.
7. The track-and-hold amplifier circuit according to claim 1 , wherein the isolation circuit further comprises a switch directly connected between the fourth node and the ground node.
8. The track-and-hold amplifier circuit according to claim 1 , wherein the isolation circuit comprises:
a third transistor comprising:
a first terminal connected to the second capacitor terminal at the third node;
a second terminal:
connected to the fourth node; and
selectively connected to the ground node; and
a third terminal coupled to a dynamic voltage.
9. The track-and-hold amplifier circuit according to claim 8 , wherein the isolation circuit further comprises a second current source directly connected to the third node.
10. The track-and-hold amplifier circuit according to claim 1 , wherein the isolation circuit further comprises a clamp device connected between the cascode circuit and the ground node.
11. The track-and-hold amplifier circuit according to claim 1 , wherein the gain setting circuit comprises: a first impedance element connected in series with a second impedance element at the second node, and wherein a series capacitance value of the first and second impedance elements is less than a capacitance value of the track-and-hold capacitor.
12. A system, comprising:
a plurality of pixel columns;
a plurality of track-and-hold amplifier circuits, wherein:
each pixel column is connected to one track-and-hold amplifier circuit from the plurality of track-and-hold amplifier circuits; and
each track-and-hold amplifier circuit comprises:
a gain setting circuit configured to receive an input signal;
a cascode circuit connected to the gain setting circuit at a first node and a second node;
a track-and-hold capacitor comprising:
a first capacitor terminal connected to an output node, wherein the output node is selectively connected to the first node; and
a second capacitor terminal; and
an isolation circuit connected to:
the second capacitor terminal at a third node;
the cascode circuit at a fourth node; and
a ground node.
13. The system according to claim 12 , further comprising a ramp analog-to-digital converter configured to receive an output signal from each track-and-hold amplifier circuit at the output node.
14. The system according to claim 12 , wherein the isolation circuit comprises:
a clamp device connected between the fourth node and the ground node; and
a switch connected between the fourth node and the ground node.
15. The system according to claim 12 , wherein the isolation circuit comprises:
a transistor comprising:
a first terminal connected to the second capacitor terminal at the third node;
a second terminal:
connected to the fourth node; and
selectively connected to the ground node; and
a third terminal coupled to a dynamic voltage.
16. The system according to claim 12 , wherein the isolation circuit further comprises a current source directly connected to the third node.
17. A track-and-hold amplifier circuit, comprising:
a gain setting circuit configured to receive an input signal;
a cascode circuit connected to the gain setting circuit at a first node and a second node;
a track-and-hold capacitor comprising:
a first capacitor terminal connected to an output node, wherein the output node is selectively connected to the first node; and
a second capacitor terminal; and
an isolation circuit comprising:
a transistor connected to:
the second capacitor terminal at a third node; and
the cascode circuit at a fourth node; and
a clamp device connected to:
the fourth node; and
a ground node; and
a switch connected between the fourth node and the ground node.
18. The track-and-hold amplifier circuit according to claim 17 , wherein the track-and-hold amplifier circuit further comprises a first current source directly connected to the first node.
19. The track-and-hold amplifier circuit according to claim 17 , wherein the isolation circuit further comprises a second current source directly connected to the third node.