Semiconductor device
A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal.
1. A semiconductor device comprising:
a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal in the case where a select signal has a first logic level;
a second buffer circuit suitable for generating a second internal chip select signal by buffering the chip select signal in the case where the select signal has a second logic level;
a detection pulse generation circuit suitable for generating a detection pulse in response to the second internal chip select signal; and
a buffer control circuit suitable for generating a buffer control signal in response to the detection pulse.
2. The semiconductor device according to claim 1 , wherein the select signal is generated by delaying the buffer control signal by a predetermined delay period.
3. The semiconductor device according to claim 1 , wherein the first buffer circuit comprises:
a current mirror suitable for supplying current to a first node and a second node; and
a charge discharger suitable for differentially discharging charges of the first node and charges of the second node depending on a logic level of the chip select signal.
4. The semiconductor device according to claim 1 , wherein the second buffer circuit comprises:
an input driver suitable for driving an input node in response to the select signal and the chip select signal; and
an output driver suitable for driving an output node through which the second internal chip select signal is outputted, in response to a signal of the input node.
5. The semiconductor device according to claim 1 , wherein the detection pulse is generated in synchronization with a predetermined edge of the second internal chip select signal.
6. The semiconductor device according to claim 1 , wherein the buffer control signal has a first logic level in the case where a power-down mode signal is enabled, and has a second logic level in the case where the detection pulse is generated.
7. The semiconductor device according to claim 1 , further comprising:
a command address buffer circuit suitable for generating an internal command address by buffering a command address in response to the buffer control signal.