IP Library Granted Patent US 11,107,947
Granted Patent B2
US 11,107,947 · App. 16/447,050 · Granted Aug 31, 2021

Micro light emitting diode

Inventors: Long Yang (Union City, CA); Chao-Kun Lin (San Jose, CA)
Assignee: Long Yang
H01L33/0093H01L25/0753H01L33/12H01L33/16H01L33/30H01L33/32H01L33/405H01L33/62H01L22/14H01L33/007H01L33/06H01L33/44H01L2933/0016H01L2933/0025H01L2933/0066
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Quick Facts
Patent No.
US 11,107,947
App. No.
16/447,050
Granted
Aug 31, 2021
Kind
B2
Abstract

Embodiments generally relate to micro-device arrays. In some embodiments, an array comprises a substrate and a plurality of micro-devices. Each micro-device is suspended over a cavity in the substrate by at least one lateral hinge attached to a side post formed into the substrate. Each micro-device comprises a bonding layer; a metal contact; semiconductor device layers; and a buffer layer. The semiconductor device layers may comprise GaN-based LED layers; wherein the buffer layer comprises AlGaN; and wherein the substrate comprises (111) oriented Silicon. In other cases, the semiconductor device layers may comprise InGaAsP-based LED layers; wherein the buffer layer comprises InGaP; and wherein the substrate comprises GaAs.

Claims (42)

1. An array comprising:

a substrate; and

a plurality of micro-devices;

wherein each micro-device is suspended over a cavity in the substrate by at least one lateral hinge attached to a side post formed into the substrate; and

wherein each micro-device comprises:

a bonding layer;

a metal contact;

semiconductor device layers; and

a buffer layer.

2. The array of claim 1 ,

wherein the semiconductor device layers comprise GaN-based LED layers;

wherein the buffer layer comprises AlGaN; and

wherein the substrate comprises (111) oriented Silicon.

3. The array of claim 1 ,

wherein the semiconductor device layers comprise InGaAsP-based LED layers;

wherein the buffer layer comprises InGaP; and

wherein the substrate comprises GaAs.

4. The array of claim 1 ,

wherein the semiconductor device layers comprise CMOS layers;

wherein the buffer layer comprises SiO2; and

wherein the substrate comprises (100) oriented Silicon.

5. The array of claim 1 ,

wherein the side posts are positioned between adjacent micro-devices.

6. The array of claim 1 ,

wherein the cross-section shape of each side post is one of round, square and rectangular.

7. The array of claim 1 ,

wherein one of the side posts is shaped as a long wall positioned between two rows of micro-devices.

8. The array of claim 1 ,

wherein side posts of different cross-section shapes are present in the array.

9. The array of claim 1 ,

wherein the bonding layer consists of either one metal or a metal stack; and

wherein the bonding layer has a melting temperature below 500 C.

10. The array of claim 1 ,

wherein the bonding layer is configured to form solder balls after melting.

11. The array of claim 1 ,

wherein each lateral hinge is configured to be broken if and when a micro-device attached to that hinge is forcibly pushed towards the substrate.

12. The array of claim 1 ,

wherein the substrate is an epitaxial substrate.

13. The array of claim 2 ,

wherein the metal contact is optically reflective, with a reflectivity greater than 70%.

14. The array of claim 3 ,

wherein the metal contact is optically reflective, with a reflectivity greater than 70%.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2021
From: RAYSENT TECHNOLOGIES INC
To: YANG, LONG
Reel/Frame 055127/0298 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2019
From: YANG, LONG; LIN, CHAO-KUN
To: RAYSENT TECHNOLOGIES INC
Reel/Frame 049556/0886 →
Continuity (2)
Provisional Application 62695962 · Jul 10, 2018
Related Publication 20200020825A1 · Jan 16, 2020