Semiconductor device and structure
A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns.
1. A 3D semiconductor device, comprising:
a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect,
wherein said first die has a first die area and said second die has a second die area,
wherein said first die area is at least 10% larger than said second die area,
wherein said second die is aligned to said first die with less than 400 nm alignment error, and
wherein said second die has a thickness of less than four microns.
2. The 3D semiconductor device according to claim 1 ,
wherein said second die comprises at least two alignment marks positioned close to said second die edge.
3. The 3D semiconductor device according to claim 1 , further comprising:
a third die directly overlaying said first die, wherein said third die is pretested.
4. The 3D semiconductor device according to claim 1 , further comprising:
a through second die via having a diameter of less than 400 nm.
5. The 3D semiconductor device according to claim 1 , further comprising:
a third die directly overlaying said first die.
6. The 3D semiconductor device according to claim 1 ,
wherein said second die is a pretested.
7. A 3D semiconductor device, comprising:
a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect,
wherein said first die is sourced from a first wafer with a diameter greater than 280 mm and said second die is sourced from a second wafer with a diameter less than 240 mm,
wherein said second die is aligned to said first die with less than 400 nm alignment error, and
wherein said second die has a thickness of less than four microns.
8. The 3D semiconductor device according to claim 7 ,
wherein said first die has a first die area and said second die has a second die area, and
wherein said first die area is at least 10% larger than said second die area.
9. The 3D semiconductor device according to claim 7 ,
wherein said second die comprises at least two alignment marks positioned close to said second die edge.
10. The 3D semiconductor device according to claim 7 , further comprising:
a third die directly overlaying said first die,
wherein said third die is pretested.
11. The 3D semiconductor device according to claim 7 , further comprising:
a through second die via having a diameter of less than 400 nm.
12. The 3D semiconductor device according to claim 7 , further comprising:
a third die directly overlaying said first die.
13. The 3D semiconductor device according to claim 7 ,
wherein said second die is a pretested.
14. A 3D semiconductor device, comprising:
a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect,
wherein said first die has a first die area and said second die has a second die area,
wherein said first die area is at least 10% larger than said second die area,
wherein said second die is aligned to said first die with less than 400 nm alignment error, and
wherein said second die has a thickness of less than four microns; and
a third die directly overlaying said first die,
wherein said third die is pretested.
15. The 3D semiconductor device according to claim 14 ,
wherein said first die is sourced from a first wafer with a diameter greater than 280 mm and said second die is sourced from a second wafer with a diameter less than 240 mm.
16. The 3D semiconductor device according to claim 14 ,
wherein said second die comprises at least two alignment marks positioned close to said second die edge.
17. The 3D semiconductor device according to claim 14 ,
wherein said third die is aligned to said first die with less than 400 nm alignment error.
18. The 3D semiconductor device according to claim 14 , further comprising:
a through second die via having a diameter of less than 400 nm.
19. The 3D semiconductor device according to claim 14 ,
wherein said third die comprises third transistors and third interconnect.
20. The 3D semiconductor device according to claim 14 ,
wherein said second die is a pretested.