Body tie optimization for stacked transistor amplifier

1. A circuital arrangement comprising:

a transistor stack configured to operate as a radio frequency (RF) amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor for receiving an input RF signal to the amplifier, and an output transistor for outputting an output RF signal that is an amplified version of the input RF signal; the transistor stack configured to operate between a supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor;

one or more gate capacitors each connected between a gate of a transistor of the plurality of stacked transistors, except the input transistor, and a reference ground, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor,

wherein at least one transistor of the plurality of stacked transistors is a four-terminal transistor having a body and a source, wherein the body is coupled to the source, and

wherein at least one transistor of the plurality of stacked transistors is a three-terminal transistor.

2. The circuital arrangement according to claim 1 , wherein the body of the at least one transistor is directly connected to the source of said transistor.

3. The circuital arrangement according to claim 1 , wherein the body of the at least one transistor is coupled to the source of said transistor via a resistor.

4. The circuital arrangement according to claim 1 , wherein the body of the at least one transistor is coupled to the source of said transistor through an impedance of a corresponding body tie.

5. The circuital arrangement according to claim 1 , wherein the one or more gate capacitors are configured to equalize an output RF voltage at a drain of the output transistor across the plurality of stacked transistors.

6. The circuital arrangement according to claim 1 , wherein the at least one transistor of the plurality of stacked transistors further comprises the output transistor.

7. The circuital arrangement according to claim 1 , wherein the at least one transistor of the plurality of stacked transistors further comprises a transistor arranged between the input transistor and the output transistor.

8. The circuital arrangement according to claim 1 , wherein the at least one transistor of the plurality of stacked transistors is the plurality of stacked transistors except the three-terminal transistor.

9. The circuital arrangement according to claim 1 , wherein the plurality of transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

10. The circuital arrangement according to claim 9 , wherein the plurality of transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

11. The circuital arrangement according to claim 9 , wherein the plurality of transistors are one of: a) N-type transistors, and b) P-type transistors.

12. The circuital arrangement according to claim 1 , wherein the supply voltage is configured to vary under control of a control signal.

13. An electronic module comprising the circuital arrangement of claim 1 .

14. An electronic system comprising the electronic module of claim 13 , wherein the electronic system comprises one of: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.

15. A method for manufacturing a radio frequency (RF) amplifier, the method comprising:

providing a substrate comprising one of: a) silicon-on-insulator substrate, and b) a silicon-on-sapphire substrate; and

manufacturing, on the substrate, a transistor stack configured to operate as a radio frequency (RF) amplifier, the transistor stack comprising:

a plurality of series connected transistors comprising at least one four-terminal transistor and at least one three-terminal transistor; and

one or more gate capacitors each connected between a gate of a transistor of the plurality of series connected transistors, except an input transistor, and a reference ground, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor,

wherein the least one four-terminal transistor has a body and a source, wherein the body is coupled to the source, the at least one four-terminal transistor comprising the input transistor.

16. The method according to claim 15 , wherein the body of the at least one four-terminal transistor is directly connected to the source of said transistor.

17. The method according to claim 15 , wherein the body of the at least one four-terminal transistor is coupled to the source of said transistor via a resistor.

18. The method according to claim 15 , wherein the body of the at least one four-terminal transistor is coupled to the source of said transistor through an impedance of a corresponding body tie.

19. The method according to claim 15 , wherein the at least one four-terminal transistor further comprises an output transistor of the amplifier.

20. The method according to claim 15 , wherein the at least one four-terminal transistor is all the transistors of the plurality of series connected transistors except the at least one three-terminal transistor.

21. A method for improving a performance of a radio frequency (RF) amplifier, the method comprising:

providing a plurality of floating body devices;

configuring the plurality of floating body devices as a cascoded stack comprising an input floating body device and cascode floating body devices;

coupling gate capacitors between gates of the cascode floating body devices and a reference ground, the gate capacitors configured to allow gate voltages at said gates to vary along with radio frequency (RF) voltages at drains of the cascode floating body devices;

based on the configuring and the coupling, obtaining an RF amplifier having a characteristic performance;

replacing, in the cascoded stack, at least one floating body device of the plurality of floating body devices with a body tied device while leaving at least one of the plurality of floating body devices in the cascoded stack, the at least one floating body device comprising the input transistor, wherein a body of the body tied device is coupled to a source of the body tied device;

based on the replacing, obtaining an RF amplifier having an improved characteristic performance; and

fabricating the RF amplifier with improved characteristic performance on one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

22. The method according to claim 21 , wherein the body of the body tied device is directly connected to the source of said device.

23. The method according to claim 21 , wherein the body of the body tied device is coupled to the source of said device via a resistor.

24. The method according to claim 21 , wherein the body of the body tied device is coupled to the source of said device through an impedance of a corresponding body tie.

25. The method according to claim 21 , wherein the replacing improves a power added efficiency (PAE) of the RF amplifier.

26. The method according to claim 21 , wherein the replacing reduces a leakage current of the RF amplifier.

27. The method according to claim 21 , wherein the replacing further comprises replacing an output transistor of the cascoded stack with a respective body tied device to improve a withstand voltage capability of the output transistor.

28. The method according to claim 21 , wherein the replacing comprises replacing all of the plurality of floating body devices except the at least one of the plurality of floating body devices with respective body tied devices to improve a transient response of the RF amplifier.

29. A method for reducing a stack height of an RF amplifier, the method comprising:

providing a level of a voltage across a stack;

providing a withstand voltage capability of a three-terminal device;

based on the level of the voltage and the withstand voltage capability, determining a height of the stack based on a required number of series connected three-terminal devices in the stack;

replacing at least one device of the series-connected three-terminal devices with a four-terminal device while leaving at least one of the series connected three-terminal devices in the stack, the at least one device comprising an input transistor of the stack, wherein a body of the four-terminal device is coupled to a source of the four-terminal device;

based on the replacing, reducing the height of the stack; and

fabricating the RF amplifier with reduced stack height on one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS),

wherein the fabricating includes coupling of gate capacitors between gates of transistors of the stack and a reference ground, the gate capacitors configured to allow gate voltages at said gates to vary along with radio frequency (RF) voltages at drains of said transistors.

30. The method according to claim 29 , wherein the body of the four-terminal device is directly connected to the source of said device.

31. The method according to claim 29 , wherein the body of the four-terminal device is coupled to the source of said device via a resistor.

32. The method according to claim 29 , wherein the body of the four-terminal device is coupled to the source of said device through an impedance of a corresponding body tie.