Fabrication of field effect transistors with ferroelectric materials
A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.
1. A method of fabricating a semiconductor device, comprising:
removing a dummy gate stack to form a first trench between gate spacers, wherein the first trench exposes a semiconductor layer;
forming a sacrificial layer along sidewalls of the gate spacers in the first trench, wherein the semiconductor layer is exposed in the first trench between portions of the sacrificial layer;
forming a first hafnium-containing gate dielectric layer along the semiconductor layer but not along the sacrificial layer in the first trench;
removing the sacrificial layer to form a second trench within the first trench, wherein a first sidewall of the second trench is defined by one of the gate spacers and a second sidewall of the second trench is defined by the first hafnium-containing gate dielectric layer;
forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and along the sidewalls of the gate spacers to fill the second trench;
annealing the first and the second hafnium-containing gate dielectric layers, wherein the annealing includes simultaneously applying an electric field; and
forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.
2. The method of claim 1 , wherein forming the sacrificial layer includes selectively depositing the sacrificial layer along the sidewalls of the gate spacers but not along the semiconductor layer.
3. The method of claim 1 , wherein forming the sacrificial layer includes forming a layer of graphene.
4. The method of claim 1 , further comprising forming an interfacial layer over the semiconductor layer after forming the sacrificial layer and before forming the first hafnium-containing gate dielectric layer.
5. The method of claim 1 , wherein the electric field is a first electric field, and wherein forming the first hafnium-containing gate dielectric layer includes simultaneously applying a second electric field.
6. The method of claim 1 , wherein the electric field is a first electric field, and wherein forming the second hafnium-containing gate dielectric layer includes simultaneously applying a second electric field.
7. The method of claim 1 , wherein annealing the first and the second hafnium-containing gate dielectric layers increases an amount of ferroelectric orthorhombic phase of a hafnium-containing material included in the first and the second hafnium-containing gate dielectric layers.
8. The method of claim 1 , wherein the second hafnium-containing gate dielectric layer is formed to directly contact the semiconductor layer.
9. A method of fabricating a semiconductor device, comprising:
removing a dummy gate stack disposed over a semiconductor layer and interposed between gate spacers to form a gate trench;
selectively depositing a sacrificial layer along sidewall surfaces of the gate spacers but not along the semiconductor layer in the gate trench;
after forming the sacrificial layer, depositing a hafnium-containing dielectric material along the semiconductor layer but not along the sacrificial layer to form a first gate dielectric layer in the gate trench, wherein the depositing includes applying a first electric field;
after forming the first gate dielectric layer, removing the sacrificial layer to expose the sidewall surfaces of the gate spacers in the gate trench;
after removing the sacrificial layer, depositing the hafnium-containing dielectric material along the exposed sidewall surfaces of the gate spacers in the gate trench to form a second gate dielectric layer, wherein the depositing includes applying a second electric field;
applying an annealing treatment to the first and the second gate dielectric layers, wherein the applying increases degree of ferroelectricity of the first and the second gate dielectric layers; and
after applying the annealing treatment, forming a metal gate electrode over the first and the second gate dielectric layers.
10. The method of claim 9 , wherein forming the sacrificial layer includes forming a self-assembled monolayer.
11. The method of claim 9 , further comprising performing a cleaning process to the semiconductor layer before forming the sacrificial layer.
12. The method of claim 9 , wherein applying the annealing treatment includes applying a third electric field to the first and the second gate dielectric layers, and wherein the first, the second, and the third electric fields are applied in a same magnitude and in a same direction with respect to the semiconductor layer.
13. The method of claim 9 , wherein removing the sacrificial layer includes applying a solvent of sulfuric acid, hydrogen peroxide, or a combination thereof.
14. The method of claim 9 , wherein a thickness of the second gate dielectric layer is less than a thickness of the first gate dielectric layer.
15. A method of fabricating a semiconductor device, comprising:
forming a dummy gate stack over a semiconductor layer protruding from a substrate;
forming gate spacers on sidewalls of the dummy gate stack;
removing the dummy gate stack to form a gate trench defined by the gate spacers;
depositing a sacrificial layer along the sidewalls but not along a bottom surface of the gate trench;
forming an interfacial layer over the bottom surface of the gate trench and between portions of the sacrificial layer;
depositing a first hafnium-containing layer over the interfacial layer;
selectively removing the sacrificial layer with respect to the first hafnium-containing layer and the interfacial layer, thereby forming an opening in the gate trench to expose the sidewalls of the gate spacers, sidewalls of the first hafnium-containing layer, and sidewalls of the interfacial layer;
depositing a second hafnium-containing layer on the first hafnium-containing layer and along the exposed sidewalls of the gate spacers in the gate trench, wherein the second hafnium-containing layer fills the opening to extend below a top surface of the interfacial layer;
annealing the first and the second hafnium-containing layers, wherein the annealing includes simultaneously applying an electric field; and
forming a metal gate electrode over the anneal first and second hafnium-containing layers to fill the gate trench.
16. The method of claim 15 , wherein the electric field is a first electric field, and wherein depositing the first hafnium-containing layer includes simultaneously applying a second electric field.
17. The method of claim 15 , wherein the electric field is a first electric field, and wherein depositing the second hafnium-containing layer includes simultaneously applying a second electric field.
18. The method of claim 15 , wherein depositing the second hafnium-containing layer results in the second hafnium-containing layer to directly contact the semiconductor layer.
19. The method of claim 15 , wherein depositing the sacrificial layer includes depositing a layer of graphene or a self-assembled monolayer.
20. The method of claim 15 , wherein the first and the second hafnium-containing layers include hafnium oxide, and wherein annealing the first and the second hafnium-containing layers increases an amount of ferroelectric orthorhombic phase of the hafnium oxide in the first and the second hafnium-containing layers.