Logic gate designs for 3D monolithic direct stacked VTFET
Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET 1 ) sharing a fin with at least one bottom VTFET (VTFET 2 ); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.
1. A logic gate device, comprising:
at least one top vertical transport field-effect transistor (VTFET 1 ) sharing a fin with at least one bottom VTFET (VTFET 2 );
a power rail connected to a power contact of the logic gate device; and
a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device,
wherein the VTFET 1 comprises a first top VTFET (VTFET 1 A) and a second top VTFET (VTFET 1 B), and the VTFET 2 comprises a first bottom VTFET (VTFET 2 A) and a second bottom VTFET (VTFET 2 B), wherein the VTFET 1 A and the VTFET 2 A share a first fin, and the VTFET and the VTFET 2 B share a second fin, and wherein the ground contact is connected to top source and drains of the VTFET 2 A.
2. The logic gate device of claim 1 , wherein the VTFET 1 is an n-channel FET (NFET) and the VTFET 2 is a p-channel FET (PFET).
3. The logic gate device of claim 1 , wherein the VTFET 1 is a PFET and the VTFET 2 is an NFET.
4. The logic gate device of claim 1 , wherein the VTFET 1 and the VTFET 2 each comprises a gate alongside the fin.
5. The logic gate device of claim 1 , further comprising:
an output contact connected to i) bottom source and drains of the VTFET 1 A and the VTFET 1 B, and ii) top source and drains of the VTFET 2 B.
6. A logic gate device, comprising:
at least one top vertical transport field-effect transistor (VTFET 1 ) sharing a fin with at least one bottom VTFET (VTFET 2 ), wherein the VTFET 1 is either a) an NFET if the VTFET 2 is a PFET or b) a PFET if the VTFET 2 is an NFET;
a power rail connected to a power contact of the logic gate device; and
a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device,
wherein the VTFET 1 comprises a first top VTFET (VTFET 1 A) and a second top VTFET (VTFET 1 B), and the VTFET 2 comprises a first bottom VTFET (VTFET 2 A) and a second bottom VTFET (VTFET 2 B), wherein the VTFET 1 A and the VTFET 2 A share a first fin, and the VTFET 1 B and the VTFET 2 B share a second fin, and wherein the ground contact is connected to top source and drains of the VTFET 2 A.
7. The logic gate device of claim 6 , wherein the VTFET 1 and the VTFET 2 each comprises a gate alongside the fin.
8. The logic gate device of claim 6 , further comprising:
an output contact connected to i) bottom source and drains of the VTFET 1 A and the VTFET 1 B, and ii) top source and drains of the VTFET 2 B.
9. A logic gate device, comprising:
at least one top vertical transport field-effect transistor (VTFET 1 ) sharing a fin with at least one bottom VTFET (VTFET 2 );
a power rail connected to a power contact of the logic gate device; and
a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device, wherein the VTFET 1 comprises a first top VTFET (VTFET 1 A′) and a second top VTFET (VTFET 1 B′), and the VTFET 2 comprises a first bottom VTFET (VTFET 2 A′) and a second bottom VTFET (VTFET 2 B′), wherein the VTFET 1 A′ and the VTFET 2 A′ share a first fin, and the VTFET 1 B′ and the VTFET 2 B′ share a second fin, and wherein the ground contact is connected to bottom source and drains of the VTFET 2 A′ and the VTFET 2 B′.
10. The logic gate device of claim 9 , further comprising:
an output contact connected to i) top source and drains of the VTFET 1 B′, and ii) top source and drains of the VTFET 2 A′ and the VTFET 2 B′.
11. The logic gate device of claim 9 , wherein the power contact is connected to i) bottom source and drains of the VTFET 1 A′ and the VTFET 1 B′, and ii) top source and drains of the VTFET 1 A′.