Combined SHA2 and SHA3 based XMSS hardware accelerator

1. An apparatus, comprising:

a computer readable memory;

an XMSS operations logic to manage XMSS functions;

a chain function controller to manage chain function algorithms;

a secure hash algorithm-2 (SHA2) accelerator;

a secure hash algorithm-3 (SHA3) accelerator, wherein:

the SHA3 accelerator is configurable to perform a SHAKE-128 function or to perform a SHAKE-256 operation; and

the SHA3 accelerator comprises:

a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and

logic to:

receive a 256 bit message input;

perform a set of 24 SHA3 rounds; and

generate a 128 bit output; and

a register bank shared between the SHA2 accelerator and the SHA3 accelerator.

2. The apparatus of claim 1 , further comprising logic to:

receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and

determine a selected accelerator from at least one of the SHA2 accelerator or the SHA3 accelerator;

apply the set of inputs to the selected accelerator.

3. The apparatus of claim 2 , further comprising logic to:

assert a busy signal on a communication bus; and

switch to a protected mode in which external read/write operations are disregarded.

4. The apparatus of claim 3 , further comprising logic to:

determine whether the XMSS operation utilizes a one-time signature function, and in response to a determination that the XMSS operation requires a one-time signature function, to:

apply a one-time signature function process to the set of XMSS inputs; and

invoke the chain function controller to apply a chain function to facilitate the one-time signature function.

5. The apparatus of claim 1 , wherein the SHA2 accelerator comprises a 64 bit datapath that is configurable to perform a single SHA2-512 round of operations or to perform two SHA2-256 rounds of operation in parallel.

6. The apparatus of claim 5 , wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively apply a carry operation when the SHA2 accelerator is configured to perform two SHA2-256 rounds of operation in parallel.

7. The apparatus of claim 5 , wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively terminate a carry operation when the SHA2 accelerator is configured to a single SHA2-512 round of operation.

8. The apparatus of claim 1 , wherein the SHA3 accelerator comprises:

a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and

logic to:

receive a 512 bit message input;

perform two sets of 24 SHA3 rounds; and

generate a 256 bit output.

9. An electronic device, comprising:

a processor; and

a hardware accelerator for an authentication logic, the hardware accelerator comprising:

a computer readable memory;

an XMSS operations logic to manage XMSS functions;

a chain function controller to manage chain function algorithms;

a secure hash algorithm-2 (SHA2) accelerator;

a secure hash algorithm-3 (SHA3) accelerator, wherein:

the SHA3 accelerator is configurable to perform a SHAKE-128 function or to perform a SHAKE-256 operation; and

the SHA3 accelerator comprises:

a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and

logic to:

receive a 256 bit message input;

perform a set of 24 SHA3 rounds; and

generate a 128 bit output; and

a register bank shared between the SHA2 accelerator and the SHA3 accelerator.

10. The electronic device of claim 9 , the hardware accelerator further comprising logic to:

receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation;

determine a selected accelerator from at least one of the SHA2 accelerator or the SHA3 accelerator; and

apply the set of inputs to the selected accelerator.

11. The electronic device of claim 10 , the hardware accelerator further comprising logic to:

assert a busy signal on a communication bus; and

switch to a protected mode in which external read/write operations are disregarded.

12. The electronic device of claim 11 , the hardware accelerator further comprising logic to:

determine whether the XMSS operation utilizes a one-time signature function, and in response to a determination that the XMSS operation requires a one-time signature function, to:

apply a one-time signature function process to the set of XMSS inputs; and

invoke the chain function controller to apply a chain function to facilitate the one-time signature function.

13. The electronic device of claim 9 , wherein the SHA2 accelerator comprises a 64 bit datapath that is configurable to perform a single SHA2-512 round of operations or to perform two SHA2-256 rounds of operation in parallel.

14. The electronic device of claim 13 , wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively apply a carry operation when the SHA2 accelerator is configured to perform two SHA2-256 rounds of operation in parallel.

15. The electronic device of claim 13 , wherein the SHA2 accelerator comprises a conditional carry propagation circuitry to selectively terminate a carry operation when the SHA2 accelerator is configured to a single SHA2-512 round of operation.

16. The electronic device of claim 9 , wherein the SHA3 accelerator comprises:

a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation; and

logic to:

receive a 512 bit message input;

perform two sets of 24 SHA3 rounds; and

generate a 256 bit output.