GPU chiplets using high bandwidth crosslinks

1. A system, comprising:

a central processing unit (CPU) communicably coupled to a first graphics processing unit (GPU) chiplet of a GPU chiplet array, wherein the GPU chiplet array includes:

the first GPU chiplet communicably coupled to the CPU via a bus; and

a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink, wherein the passive crosslink is dedicated for inter-chiplet communications.

2. The system of claim 1 , wherein the passive crosslink comprises a passive interposer die.

3. The system of claim 1 , wherein the first GPU chiplet comprises a first PHY region including conductor structures for chiplet-to-chiplet communications, and further wherein the second GPU chiplet comprises a second PHY region including conductor structures for chiplet-to-chiplet communications.

4. The system of claim 3 , further comprising:

a third GPU chiplet communicably coupled to the first GPU chiplet via the passive crosslink, wherein the third GPU chiplet comprises a third PHY region including conductor structures for chiplet-to-chiplet communications.

5. The system of claim 4 , wherein the first PHY region of the first GPU chiplet comprises a first passive crosslink PHY including conductor traces solely for communications between the passive crosslink and a last level cache of the first GPU chiplet.

6. The system of claim 4 , wherein:

the second PHY region of the second GPU chiplet comprises a second passive crosslink PHY including conductor traces solely for communications between the passive crosslink and a last level cache of the second GPU chiplet; and

the third PHY region of the third GPU chiplet comprises a third passive crosslink PHY including conductor traces solely for communications between the passive crosslink and a last level cache of the third GPU chiplet.

7. The system of claim 1 , wherein the passive crosslink communicably couples all GPU chiplets in the GPU chiplet array.

8. The system of claim 1 , further comprising:

a first cache memory hierarchy at the first GPU chiplet, wherein a first level of the first cache memory hierarchy is coherent within the first GPU chiplet; and

a second cache memory hierarchy at the second GPU chiplet, wherein a first level of the second cache memory hierarchy is coherent within the second GPU chiplet.

9. The system of claim 8 , further comprising:

a unified cache memory including both a last level of the first cache memory hierarchy and a last level of the second cache memory hierarchy, wherein the unified cache memory is coherent across all GPU chiplets of the GPU chiplet array.

10. The system of claim 1 , further comprising:

a plurality of conductive pillars coupling a circuit board substrate to a first non-PHY region of the first GPU chiplet and a second non-PHY region of the second GPU chiplet.

11. A method, comprising:

receiving, at a first GPU chiplet of a GPU chiplet array, a memory access request from a central processing unit (CPU);

determining, at a passive crosslink controller of the first GPU chiplet, a caching GPU chiplet corresponding to a location at which data associated with the memory access request is stored;

routing, via a passive crosslink dedicated for inter-chiplet communications in the GPU chiplet array, the memory access request to a last level cache of the caching GPU chiplet; and

returning the data associated with the memory access request to the CPU.

12. The method of claim 11 , wherein routing the memory access request further includes a scalable data fabric requesting the data associated with the memory access request from the caching GPU chiplet.

13. The method of claim 11 , wherein routing the memory access request to the last level cache of the caching GPU chiplet further comprises:

routing, based on determining the first GPU chiplet is the caching GPU chiplet, the memory access request via a first passive crosslink PHY including conductor traces solely for communications between the passive crosslink and the last level cache of the first GPU chiplet.

14. The method of claim 11 , wherein routing the memory access request to the last level cache of the caching GPU chiplet further comprises:

routing, based on determining a second GPU chiplet is the caching GPU chiplet, the memory access request via a second passive crosslink PHY including conductor traces solely for communications between the passive crosslink and the last level cache of the second GPU chiplet.

15. The method of claim 11 , further comprising:

returning the data associated with the memory access request to the first GPU chiplet via a passive crosslink PHY including conductor traces solely for communications between the passive crosslink and the caching GPU chiplet.

16. A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:

receive, at a first GPU chiplet of a GPU chiplet array, a memory access request from a central processing unit (CPU);

determine, at a passive crosslink controller of the first GPU chiplet, a caching GPU chiplet corresponding to a location at which data associated with the memory access request is stored;

route, via a passive crosslink dedicated for inter-chiplet communications in the GPU chiplet array, the memory access request to a last level cache of the caching GPU chiplet; and

return the data associated with the memory access request to the CPU.

17. The non-transitory computer readable medium of claim 16 , the set of executable instructions further to manipulate at least one processor to: request, via a scalable data fabric, the data associated with the memory access request from the caching GPU chiplet.

18. The non-transitory computer readable medium of claim 16 , the set of executable instructions further to manipulate at least one processor to:

route, based on determining the first GPU chiplet is the caching GPU chiplet, the memory access request via a first passive crosslink PHY including conductor traces solely for communications between the passive crosslink and the last level cache of the first GPU chiplet.

19. The non-transitory computer readable medium of claim 16 , the set of executable instructions further to manipulate at least one processor to:

route, based on determining a second GPU chiplet is the caching GPU chiplet, the memory access request via a second passive crosslink PHY including conductor traces solely for communications between the passive crosslink and the last level cache of the second GPU chiplet.

20. The non-transitory computer readable medium of claim 16 , the set of executable instructions further to manipulate at least one processor to:

return the data associated with the memory access request to the first GPU chiplet via a passive crosslink PHY including conductor traces solely for communications between the passive crosslink and the caching GPU chiplet.