Trench semiconductor device having shaped gate dielectric and gate electrode structures and method
A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g., reduced leakage and more stable breakdown voltage) and improved reliability.
1. A semiconductor device comprising:
a region of semiconductor material having a first major surface and a second major surface opposite to the first major surface;
a trench structure comprising:
a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view; and
a first conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region; and
a second conductive material having a first portion disposed adjacent the first major surface on opposing sides of the trench structure to provide a Schottky contact region, and a second portion disposed in the trench above and coupled to the first conductive material, wherein:
the Schottky contact region comprises an upper surface residing on a second horizontal plane in the cross-sectional view,
the dielectric region is disposed along opposing sidewall surfaces of the trench and disposed along a lower surface of the trench;
the dielectric region comprises a first uppermost surface;
a major portion of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view; and
at least a portion of the first uppermost surface of the dielectric region extends above an upper surface of the second portion of the second conductive material in the cross-sectional view.
2. The semiconductor device of claim 1 , wherein:
the region of semiconductor material comprises:
a semiconductor substrate; and
a semiconductor layer provided with the semiconductor substrate;
the semiconductor layer provides the first major surface;
the semiconductor layer has a different doping concentration than that of the semiconductor substrate; and
one or more of the semiconductor substrate or the semiconductor layer comprises SiGe, SiGeC, SiC, GaN, or AlGaN.
3. The semiconductor device of claim 1 , wherein:
the Schottky contact region is disposed on a mesa portion of the region of semiconductor material adjacent to the trench; and
the first uppermost surface comprises a sloped shape.
4. The semiconductor device of claim 3 , wherein:
the sloped shape comprises a first portion that steps upward from an edge of the mesa portion and upwardly slopes in a direction towards the first conductive material.
5. The semiconductor device of claim 3 , wherein:
at least a portion of the sloped shape comprises a triangular shape.
6. The semiconductor device of claim 3 , wherein:
the sloped shape comprises a trapezoid shape.
7. The semiconductor device of claim 3 , wherein:
the sloped shape further comprises a stepped portion in the cross-sectional view.
8. The semiconductor device of claim 1 , wherein:
substantially all of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view.
9. The semiconductor device of claim 1 , wherein:
the major portion of the first uppermost surface is disposed above the second horizontal plane in the cross-sectional view.
10. The semiconductor device of claim 1 , wherein:
the Schottky contact region is configured having an inward facing surface having a concave shape with respect to the first major surface.
11. The semiconductor device of claim 1 , wherein:
the Schottky contact region is configured having an inward facing surface having a convex shape with respect to the first major surface.
12. A semiconductor device comprising:
a region of semiconductor material having a first major surface and a second major surface opposite to the first major surface;
a trench structure comprising:
a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view; and
a first conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region; and
a second conductive material disposed adjacent the first major surface on opposing sides of the trench structure to provide a contact region, wherein:
a portion of the second conductive material is further disposed over and coupled to the first conductive material;
the dielectric region is disposed along opposing sidewall surfaces of the trench and disposed along a lower surface of the trench;
the dielectric region comprises a first uppermost surface;
a major portion comprising 50% or more of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view;
the portion of the second conductive material comprises an upper surface located above the first horizontal plane in the cross-sectional view;
the second conductive material is disposed on a mesa portion of the region of semiconductor material adjacent to the trench;
the first uppermost surface comprises a sloped shape; and
the sloped shape includes a portion that upwardly slopes in a direction from an edge of the mesa portion towards the second conductive material.
13. The semiconductor device of claim 12 , wherein:
the sloped shape includes a flat portion substantially parallel to the first horizontal plane.
14. The semiconductor device of claim 12 , wherein:
the sloped shape further includes a stepped portion.
15. The semiconductor device of claim 12 , wherein:
substantially all of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view.
16. The semiconductor device of claim 12 , wherein:
at least a portion of the first uppermost surface is disposed above the upper surface of the portion of the second conductive material coupled to the first conductive material.
17. A method of forming a semiconductor device, comprising:
providing a region of semiconductor material having first and second opposing major surfaces;
providing a trench structure comprising:
a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view; and
a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region; and
providing a Schottky contact region disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view, wherein:
the dielectric region is disposed along opposing sidewall surfaces of the trench and disposed along a lower surface of the trench;
the dielectric region comprises a first uppermost surface;
a major portion of the first uppermost surface is disposed above the first horizontal plane in the cross-sectional view; and
the first uppermost surface has a sloped shape in the cross-sectional view.
18. The method of claim 17 , wherein providing the trench structure comprises:
forming a first layer of material overlying surfaces of the trench and the first major surface, the first layer of material comprising a dielectric material;
forming a second layer of material overlying the first layer of material, the second layer of material comprising the conductive material, wherein the second layer of material comprises a notch extending inward from an upper surface of the second layer of material above the trench;
removing a first portion of the second layer of material using a first planarization step;
removing a second portion of the second layer of material using a second planarization step, wherein the step of removing the second portion of the second layer of material provides conductive material within the trench comprising a flared-out portion proximate to an upper surface of the conductive material; and
removing a portion of the first layer of material to expose portions of the first major surface and to provide the dielectric region.
19. The method of claim 17 , wherein:
removing the first portion of the second layer of material comprises providing the second portion of the second layer of material having a thickness of approximately 0.15 microns;
removing the first portion of the second layer of material comprises using etch planarization; and
removing the second portion of the second layer of material comprises using chemical mechanical planarization.
20. The method of claim 17 , wherein:
forming the Schottky contact region comprises forming the Schottky contact region having an upper surface defining a second horizontal plane in the cross-sectional view; and
a major portion comprising 50% or more of the uppermost surface is disposed above the second horizontal plane.