Semiconductor memory device
A semiconductor memory device of an embodiment includes a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner, a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion, and a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, in which a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where memory cells are arranged.
1. A semiconductor memory device comprising:
a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner;
a plurality of pillars extending in a stacking direction of the stacked body to penetrate the stacked body from an uppermost metal layer to a lowermost metal layer of the stacked body, and forming a plurality of memory cells at respective intersections with at least metal layers arranged near a center of the stacked body, of the plurality of metal layers;
a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion; and
a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, wherein
a coverage of the columnar portions arranged in the lowermost step is larger than a coverage of the columnar portions arranged in an upper step adjacent to the lowermost step only in a second direction toward a region where the memory cells are arranged.
2. The semiconductor memory device according to claim 1 , wherein
the coverage of the columnar portions arranged in the lowermost step is 25% or more.
3. The semiconductor memory device according to claim 2 , wherein
the coverage of the r portions is calculated on the basis of a total sum of areas occupied by the plurality of columnar portions at a same height position as an upper surface of the uppermost metal layer.
4. The semiconductor memory device according to claim 1 , wherein
a diameter of at least one of the columnar portions arranged in the lowermost step is larger than a diameter of the pillars and is 1.4 times or less the diameter of the pillars.
5. The semiconductor memory device according to claim 1 , wherein
at least one of the columnar portions has a shape having anisotropy including a longitudinal direction and a short direction in top view, and
the longitudinal direction of at least one of the columnar portions is directed to a direction along the second direction.
6. The semiconductor memory device according to claim 5 , wherein
at least one of the columnar portions has an oval shape, an elliptical shape, or a rectangular shape in top view.
7. The semiconductor memory device according to claim 5 , wherein
a ratio of the longitudinal direction to the short direction of at least one of the columnar portions is 2.0 or less.
8. The semiconductor memory device according to claim 5 , wherein
at least another one of the columnar portions has a substantially perfect circular shape in top view.
9. The semiconductor memory device according to claim 5 , wherein
a ratio of the longitudinal direction to the short direction of at least one of the columnar portions arranged in the lowermost step is larger than a ratio of a longitudinal direction to a short direction of at least one of the columnar portions arranged in the upper step adjacent to the lowermost step only in the second direction.
10. The semiconductor memory device according to claim 1 , wherein
the band portion is arranged at a position within from the leading end portion of the metal layer of the lowermost step of the stepped portion.
11. The semiconductor memory device according to claim 1 , wherein
the lowermost step of the stepped portion is arranged at a position in the second direction between the band portion and the upper step adjacent to the lowermost step only in the second direction.
12. A semiconductor memory device comprising:
a stacked body having a stepped portion in which a plurality of metal layers is stacked via an insulating layer, and end portions of the plurality of metal layers are formed in a stepwise manner;
a plurality of pillars extending in a stacking direction of the stacked body to penetrate the stacked body from an uppermost metal layer to a lowermost metal layer of the stacked body, and forming a plurality of memory cells at respective intersections with at least metal layers arranged near a center of the stacked body, of the plurality of metal layers;
a plurality of columnar portions arranged in steps of the stepped portion and penetrating the stepped portion; and
a band portion provided near a leading end portion of the metal layer of a lowermost step of the stepped portion, the band portion extending in a first direction along the leading end portion and dividing the stacked body and a peripheral region of the stacked body, wherein
a coverage of the columnar portions arranged in the lowermost step is 25% or more.
13. The semiconductor memory device according to claim 12 , wherein
the coverage of the columnar portions is calculated on the basis of a total sum of areas occupied by the plurality of columnar portions at a same height position as an upper surface of the uppermost metal layer.
14. The semiconductor memory device according to claim 12 , wherein
a diameter of at least one of the columnar portions arranged in the lowermost step is larger than a diameter of the pillars and is 1.4 times or less the diameter of the pillars.
15. The semiconductor memory device according to claim 12 , wherein
at least one of the columnar portions has a shape having anisotropy including a longitudinal direction and a short direction in top view, and
the longitudinal direction of at least one of the columnar portions is directed to a second direction orthogonal to the first direction.
16. The semiconductor memory device according to claim 15 , wherein
at least one of the columnar portions has an oval shape, an elliptical shape, or a rectangular shape in top view.
17. The semiconductor memory device according to claim 15 , wherein
a ratio of the longitudinal direction to the short direction of at least one of the columnar portions is 2.0 or less.
18. The semiconductor memory device according to claim 15 , wherein
at least another one of the columnar portions has a substantially perfect circular shape in top view.
19. The semiconductor memory device according to claim 12 , wherein
the band portion is arranged at a position within 5 μm from the leading end portion of the metal layer of the lowermost step of the stepped portion.
20. The semiconductor memory device according to claim 12 , wherein
the lowermost step of the stepped portion is arranged at a position in a second direction between the band portion and an upper step adjacent to the lowermost step only in the second direction, the second direction being orthogonal to the first direction.