Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and a stepped portion in which the plurality of conductive layers is processed in a stepped shape; and a plurality of second pillars that extends in the stacked body in the stepped portion, in which each of the plurality of second pillars includes a second insulating layer extending in the stacked body in the stacking direction, a semiconductor layer covering a side wall of the second insulating layer, a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and a fourth insulating layer disposed in contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer.
1. A semiconductor memory device comprising:
a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and includes a stepped portion in which the plurality of conductive layers is processed in a stepped shape;
a first pillar that extends in a stacking direction of the stacked body in the stacked body away from the stepped portion in a first direction intersecting the stacking direction and forms a memory cell at each intersection with at least a part of the plurality of conductive layers; and
a plurality of second pillars that extends in the stacking direction in the stacked body in the stepped portion, wherein
each of the plurality of second pillars includes
a second insulating layer extending in the stacked body in the stacking direction,
a semiconductor layer covering a side wall of the second insulating layer,
a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and
a fourth insulating layer disposed in direct contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer, and
the third and fourth insulating layers contain a same kind of material.
2. The semiconductor memory device according to claim 1 , further comprising
a first plate member and a second plate member that extend in the stacking direction and the first direction in the stacked body at positions away from each other in a second direction intersecting the stacking direction and the first direction,
wherein the plurality of second pillars is dispersedly arranged between the first and second plate members.
3. The semiconductor memory device according to claim 1 , further comprising:
a contact that is disposed in the stepped portion and connected to one of the plurality of conductive layers; and
a plurality of third pillars that extends in the stacking direction in the stacked body in the stepped portion at positions closer to the contact than the plurality of second pillars is, wherein
each of the plurality of third pillars includes
the second insulating layer extending in the stacked body in the stacking direction,
the semiconductor layer covering the side wall of the second insulating layer,
the third insulating layer disposed in contact with the side wall of the semiconductor layer and covering the side wall of the semiconductor layer,
a fifth insulating layer disposed in contact with the side wall of the third insulating layer and covering the side wall of the third insulating layer, and
the fourth insulating layer disposed in contact with a side wall of the fifth insulating layer and covering the side wall of the fifth insulating layer, and
the fifth insulating layer contains a different kind of material from that of the third and fourth insulating layers.
4. The semiconductor memory device according to claim 3 , wherein
the third and fourth insulating layers are oxide layers, and the fifth insulating layer is a nitride layer.
5. The semiconductor memory device according to claim 4 , further comprising:
a sixth insulating layer that covers upper sides of the plurality of conductive layers processed in the stepped shape in the stepped portion and has an upper surface that is substantially flush; and
a seventh insulating layer that is disposed between the plurality of conductive layers and the sixth insulating layer along the stepped shape of the plurality of conductive layers in the stepped portion, contains a same kind of material as that of the fifth insulating layer, and is penetrated by the contact together with the sixth insulating layer.
6. The semiconductor memory device according to claim 3 , wherein
the plurality of third pillars surrounds the contact when viewed from the stacking direction.
7. The semiconductor memory device according to claim 6 , further comprising
a first plate member and a second plate member that extend in the stacking direction and the first direction in the stacked body at positions away from each other in a second direction intersecting the stacking direction and the first direction, wherein
at least a part of the plurality of second pillars is arranged along the first and second plate members.
8. A semiconductor memory device comprising:
a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and includes a stepped portion in which the plurality of conductive layers is processed in a stepped shape;
a first pillar that extends in a stacking direction of the stacked body in the stacked body away from the stepped portion in a first direction intersecting the stacking direction and forms a memory cell at each intersection with at least a part of the plurality of conductive layers; and
a plurality of second pillars that extends in the stacking direction in the stacked body in the stepped portion, wherein
the first pillar includes
a second insulating layer extending in the stacked body in the stacking direction,
a semiconductor layer covering a side wall of the second insulating layer,
a third insulating layer covering a side wall of the semiconductor layer,
a fourth insulating layer covering a side wall of the third insulating layer, and
a charge accumulation layer containing a different kind of insulating material from that of the third and fourth insulating layers and interposed between the third and fourth insulating layers, and
each of the plurality of second pillars includes
the second insulating layer extending in the stacked body in the stacking direction,
the semiconductor layer covering the side wall of the second insulating layer,
the third insulating layer covering the side wall of the semiconductor layer, and
the fourth insulating layer covering the side wall of the third insulating layer without interposing the charge accumulation layer between the third and fourth insulating layers.
9. The semiconductor memory device according to claim 8 , wherein
the third and fourth insulating layers are oxide layers, and the charge accumulation layer is a nitride layer.
10. The semiconductor memory device according to claim 8 , further comprising
a first plate member and a second plate member that extend in the stacking direction and the first direction in the stacked body at positions away from each other in a second direction intersecting the stacking direction and the first direction, wherein
the plurality of second pillars is dispersedly arranged between the first and second plate members.
11. The semiconductor memory device according to claim 8 , further comprising:
a contact that is disposed in the stepped portion and connected to one of the plurality of conductive layers; and
a plurality of third pillars that extends in the stacking direction in the stacked body in the stepped portion at positions closer to the contact than the plurality of second pillars is, wherein
each of the plurality of third pillars has a same layer structure as that of the first pillar.
12. The semiconductor memory device according to claim 11 , wherein
the plurality of third pillars surrounds the contact when viewed from the stacking direction.
13. The semiconductor memory device according to claim 12 , further comprising
a first plate member and a second plate member that extend in the stacking direction and the first direction in the stacked body at positions away from each other in a second direction intersecting the stacking direction and the first direction, wherein
at least a part of the plurality of second pillars is arranged along the first and second plate members.
14. A semiconductor memory device comprising:
a stacked body that includes a plurality of conductive layers and a plurality of insulating layers alternately stacked one by one and includes a stepped portion in which the plurality of conductive layers is processed in a stepped shape;
a first pillar that extends in a stacking direction of the stacked body in the stacked body away from the stepped portion in a first direction intersecting the stacking direction and forms a memory cell at each intersection with at least a part of the plurality of conductive layers; and
a plurality of second pillars and a plurality of third pillars that extend in the stacking direction in the stacked body in the stepped portion, each of the plurality of second pillars and each of the plurality of third pillars having a different layer structure from each other, wherein
each of the plurality of third pillars includes
an oxide layer extending in the stacking direction, and
a nitride layer extending in the stacking direction at a predetermined position of an inner side of the oxide layer, and
each of the plurality of second pillars includes
one or more oxide layers extending in the stacking direction without including the nitride layer.
15. The semiconductor memory device according to claim 14 , wherein
each of the plurality of third pillars includes
a first oxide layer extending in the stacked body in the stacking direction,
a semiconductor layer covering a side wall of the first oxide layer,
a second oxide layer covering a side wall of the semiconductor layer,
a first nitride layer covering a side wall of the second oxide layer, and
a third oxide layer covering a side wall of the first nitride layer.
16. The semiconductor memory device according to claim 15 , wherein
each of the plurality of second pillars includes
the first oxide layer extending in the stacked body in the stacking direction,
the semiconductor layer covering the side wall of the first oxide layer,
the second oxide layer covering the side wall of the semiconductor layer, and
the third oxide layer covering the side wall of the second oxide layer.
17. The semiconductor memory device according to claim 15 , further comprising
a first plate member and a second plate member that extend in the stacking direction and the first direction in the stacked body at positions away from each other in a second direction intersecting the stacking direction and the first direction, wherein
at least a part of the plurality of second pillars is arranged along the first and second plate members.
18. The semiconductor memory device according to claim 15 , further comprising
a contact that is disposed in the stepped portion and connected to one of the plurality of conductive layers, wherein
the plurality of third pillars is disposed at positions closer to the contact than the plurality of second pillars is, and surrounds the contact when viewed from the stacking direction.
19. The semiconductor memory device according to claim 18 , wherein
at least a part of the plurality of second pillars surrounds the contact at positions more distant than those of the plurality of third pillars when viewed from the stacking direction.
20. The semiconductor memory device according to claim 18 , further comprising:
a fourth oxide layer that covers upper sides of the plurality of conductive layers processed in the stepped shape in the stepped portion and has an upper surface that is substantially flush; and
a second nitride layer that is disposed between the plurality of conductive layers and the fourth oxide layer along the stepped shape of the plurality of conductive layers in the stepped portion and is penetrated by the contact together with the fourth oxide layer.