IP Library › Granted Patent US 8,048,798
Granted Patent B2
US 8,048,798 · App. 12/389,977 · Granted Nov 1, 2011

Method for manufacturing a nonvolatile semiconductor storage device where memory cells are arranged three dimensionally

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,048,798
App. No.
12/389,977
Granted
Nov 1, 2011
Kind
B2
Abstract

A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer.

Claims (44)

1. A method for manufacturing a nonvolatile semiconductor storage device, comprising:

forming a first insulating layer;

forming a first conductive layer on the first insulating layer;

forming a second insulating layer on the first conductive layer;

forming a first hole so that it penetrates the first insulating layer, the first conductive layer, and the second insulating layer;

forming a first side wall insulating layer on a side wall of the first hole;

forming a sacrificing layer so that the sacrificing layer fills in the first hole;

forming a third insulating layer on an upper layer of the sacrificing layer;

forming a second conductive layer on the third insulating layer;

forming a fourth insulating layer on the second conductive layer;

forming a second hole on a position which matches with the first hole so that the second hole penetrates the third insulating layer, the second conductive layer, and the fourth insulating layer;

forming a second side wall insulating layer on a side wall of the second hole;

removing the sacrificing layer after the formation of the second side wall insulating layer; and

forming a semiconductor layer so that the semiconductor layer fills in the first hole and the second hole after the removal of the sacrificing layer.

2. The method for manufacturing a nonvolatile semiconductor storage device according to claim 1 , wherein

any one of the first conductive layer and the second conductive layer is constituted so as to serve as a control gate of an electrically rewritable memory cell,

the other one of the first conductive layer and the second conductive layer is constituted so as to serve as a control gate of a selecting transistor for controlling a voltage to be applied to the memory cell.

3. The method for manufacturing a nonvolatile semiconductor storage device according to claim 1 , wherein

the sacrificing layer is composed of amorphous silicon or silicon germanium.

4. The method for manufacturing a nonvolatile semiconductor storage device according to claim 1 , further comprising:

forming a fifth insulating layer before the step of forming the first insulating layer, the first conductive layer, and the second insulating layer;

forming a third conductive layer on the fifth insulating layer;

forming a sixth insulating layer on the third conductive layer;

forming a third hole so that it penetrates the fifth insulating layer, the third conductive layer, and the sixth insulating layer;

forming a third side wall insulating layer on a side wall of the third hole; and

forming a sacrificing layer so that it fills in the third hole,

wherein the first insulating layer, the first conductive layer, and the second insulating layer are formed on an upper layer of the sixth insulating layer,

the first hole is formed on a position which matches with the third hole.

5. The method for manufacturing a nonvolatile semiconductor storage device according to claim 4 , wherein

the first conductive layer is constituted so as to serve as a control gate of an electrically rewritable memory cell,

the second conductive layer and the third conductive layer are constituted so as to serve as control gates of a selecting transistor for controlling a voltage to be applied to the memory cell.

6. The method for manufacturing a nonvolatile semiconductor storage device according to claim 5 , further comprising:

laminating a plurality of first conductive layers in a laminated direction via a plurality of second conductive layers; and

forming end portions of the plurality of first conductive layers into a staircase pattern.

7. The method for manufacturing a nonvolatile semiconductor storage device according to claim 4 , further comprising:

laminating a plurality of first conductive layers in a laminated direction via a plurality of second conductive layers; and

covering end portions of the plurality of first conductive layers with a protection insulating layer.

8. The method for manufacturing a nonvolatile semiconductor storage device according to claim 4 , further comprising:

laminating a tunnel insulating layer, a charge accumulating layer and a block insulating layer so as to form the first side wall insulating layer, wherein

the tunnel insulating layer is formed so as to contact with a side wall of the first pillar-shaped semiconductor layer and is composed of silicon oxide,

the charge accumulating layer is formed so as to contact with the tunnel insulating layer and is composed of silicon nitride,

the block insulating layer is formed so as to contact with the charge accumulating layer and is composed of silicon oxide.

9. The method for manufacturing a nonvolatile semiconductor storage device according to claim 4 , wherein

the second side wall insulating layer and the third side wall insulating layer are composed of silicon oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2009
From: KIDOH, MASARU; KITO, MASARU; KATSUMATA, RYOTA; FUKUZUMI, YOSHIAKI; TANAKA, HIROYASU; ISHIDUKI, MEGUMI; KOMORI, YOSUKE; AOCHI, HIDEAKI; MATSUOKA, YASUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022496/0771 →
Priority Claims (1)
JP 2008-053170 · Mar 4, 2008 · national
Continuity (1)
Related Publication 20090224309A1 · Sep 10, 2009