Mesh shader output management technology

1. A computing system comprising:

a network controller;

a graphics processor coupled to the network controller, wherein the graphics processor includes internal storage and the graphics processor is to subdivide the internal storage into a plurality of full-sized buffer allocations and a plurality of partial-sized buffer allocations; and

a memory coupled to the graphics processor, the memory including a set of mesh shader instructions, which when executed by the graphics processor, cause the computing system to:

determine a size of a meshlet,

write the meshlet to a full-sized buffer allocation if the size of the meshlet is greater than a partial-sized buffer allocation, and

write the meshlet to the partial-sized buffer allocation if the size of the meshlet is not greater than the partial-sized buffer allocation.

2. The computing system of claim 1 , wherein the mesh shader instructions, when executed, cause the computing system to output the size of the meshlet and a write location indicator.

3. The computing system of claim 1 , wherein the meshlet is written to a largest available partial-sized buffer allocation.

4. The computing system of claim 1 , wherein the mesh shader instructions, when executed, cause the computing system to receive a notification of the partial-sized buffer allocation.

5. The computing system of claim 4 , wherein the mesh shader instructions, when executed, cause the computing system to generate the meshlet after receipt of the notification.

6. The computing system of claim 1 , wherein the mesh shader instructions, when executed, cause the computing system to output a null indicator if the size of the meshlet is null.

7. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

determine a size of a meshlet,

write the meshlet to a full-sized buffer allocation if the size of the meshlet is greater than a partial-sized buffer allocation, and

write the meshlet to the partial-sized buffer allocation if the size of the meshlet is not greater than the partial-sized buffer allocation.

8. The semiconductor apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to output the size of the meshlet and a write location indicator.

9. The semiconductor apparatus of claim 7 , wherein the meshlet is written to a largest available partial-sized buffer allocation.

10. The semiconductor apparatus of claim 7 , wherein the full-sized buffer allocation and the partial-sized buffer allocation are internal storage of a graphics processor.

11. The semiconductor apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to:

receive a notification of the partial-sized buffer allocation, and

generate the meshlet after receipt of the notification.

12. The semiconductor apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to output a null indicator if the size of the meshlet is null.

13. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:

determine a size of a meshlet;

write the meshlet to a full-sized buffer allocation if the size of the meshlet is greater than a partial-sized buffer allocation; and

write the meshlet to the partial-sized buffer allocation if the size of the meshlet is not greater than the partial-sized buffer allocation.

14. The at least one non-transitory computer readable storage medium of claim 13 , wherein the instructions, when executed, cause the computing system to output the size of the meshlet and a write location indicator.

15. The at least one non-transitory computer readable storage medium of claim 13 , wherein the meshlet is written to a largest available partial-sized buffer allocation.

16. The at least one non-transitory computer readable storage medium of claim 13 , wherein the full-sized buffer allocation and the partial-sized buffer allocation are internal storage of a graphics processor.

17. The at least one non-transitory computer readable storage medium of claim 13 , wherein the instructions, when executed, cause the computing system to:

receive a notification of the partial-sized buffer allocation; and

generate the meshlet after receipt of the notification.

18. The at least one non-transitory computer readable storage medium of claim 13 , wherein the instructions, when executed, cause the computing system to output a null indicator if the size of the meshlet is null.

19. A method comprising:

determining a size of a meshlet;

writing the meshlet to a full-sized buffer allocation if the size of the meshlet is greater than a partial-sized buffer allocation; and

writing the meshlet to the partial-sized buffer allocation if the size of the meshlet is not greater than the partial-sized buffer allocation.

20. The method of claim 19 , further including outputting the size of the meshlet and a write location indicator.

21. The method of claim 19 , wherein the meshlet is written to a largest available partial-sized buffer allocation.

22. The method of claim 19 , wherein the full-sized buffer allocation and the partial-sized buffer allocation are internal storage of a graphics processor.

23. The method of claim 19 , further including:

receiving a notification of the partial-sized buffer allocation; and

generating the meshlet after receipt of the notification.

24. The method of claim 19 , further including outputting a null indicator if the size of the meshlet is null.