Transistors with ferroelectric spacer and methods of fabrication
A transistor includes a semiconductor body including a material such as an amorphous or polycrystalline material, for example and a gate stack on a first portion of the body. The gate stack includes a gate dielectric on the body, and a gate electrode on the gate dielectric. The transistor further includes a first metallization structure on a second portion of the body and a third metallization structure on a third portion of the body, opposite to the second portion. The transistor further includes a ferroelectric material on at least a fourth portion of the body, where the ferroelectric material is between the gate stack and the first or second metallization structure.
1. A transistor, comprising:
a body comprising a semiconductor;
a gate stack on a first portion of the body, the gate stack comprising:
a gate dielectric on, and in direct contact with, the body; and
a gate electrode on a first portion of the gate dielectric, wherein a second portion of the gate dielectric is laterally adjacent to, and in direct contact with, a sidewall of the gate electrode;
a first metallization structure coupled to a second portion of the body;
a second metallization structure coupled to a third portion of the body, wherein the first portion is between the second portion and the third portion; and
a ferroelectric material on, and in direct contact with, at least a fourth portion of the body, the ferroelectric material between the gate stack and the first metallization structure or second metallization structure, wherein the ferroelectric material is in direct contact with a sidewall of the first or second metallization structure, wherein the ferroelectric material is in direct contact with the second portion of the gate dielectric, and wherein the fourth portion of the body and the ferroelectric material both have a lateral thickness that is substantially equal to a spacing between the gate stack and the first metallization structure or second metallization structure.
2. The transistor of claim 1 , wherein the ferroelectric material is non-amorphous and comprises oxygen and one or more of hafnium, zirconium, aluminum, lanthanum or yttrium, PZT, BaTiO3 or HfZrO 2 , oxygen and hafnium doped with one or more of Si, Gd, Y, Sr, La or Al to a dopant concentration between 0.1% and 75%.
3. The transistor of claim 1 , wherein the ferroelectric material has a composition or crystallinity that is different from that of the gate dielectric.
4. The transistor of claim 1 , wherein the lateral thickness of the ferroelectric material is greater than a thickness of the gate dielectric between the gate electrode and the body.
5. The transistor of claim 1 , wherein the semiconductor comprises a metal and oxygen.
6. The transistor of claim 1 , wherein the gate stack has a lateral thickness and wherein the lateral thickness is between 10 nm and 100 nm.
7. The transistor of claim 1 , wherein the ferroelectric material has a lateral thickness that is between 2 nm and 20 nm.
8. The transistor of claim 1 , wherein the ferroelectric material comprises:
a sidewall portion adjacent to the gate stack, the sidewall portion having a lateral thickness in a first direction;
and a lateral portion adjacent to the sidewall portion and on the body, wherein the lateral portion has a vertical thickness in a second direction, the second direction orthogonal to the first direction and wherein the vertical thickness is substantially equal to the lateral thickness.
9. The transistor of claim 8 , wherein the lateral portion has a lateral thickness in the first direction, wherein the lateral thickness of the lateral portion is greater than the lateral thickness of the sidewall portion.
10. The transistor of claim 1 , wherein the second portion of the gate dielectric has a lateral thickness in a first direction that is substantially equal to a thickness in a second direction of the first portion and wherein the ferroelectric material has a lateral thickness that is greater than the lateral thickness of the second portion.
11. A semiconductor device comprising:
the transistor of claim 1 ; and
a memory device above and coupled with the first metallization structure or the second metallization structure.
12. The semiconductor device of claim 11 , wherein the memory device comprises a resistive random-access memory (RRAM) element, the RRAM element comprising:
a bottom electrode;
a switching layer above the bottom electrode; and
a top electrode above the switching layer.
13. The semiconductor device of claim 11 , wherein the memory device comprises a magnetic tunnel junction (MTJ) device, the MTJ device comprising:
a fixed magnet;
a tunnel barrier above the fixed magnet; and
a free magnet above the tunnel barrier.