Apparatus and method for modifying addresses, data, or program code associated with offloaded instructions
Apparatus and method for Modifying Addresses, Data, or Program Code Associated With Offloaded Instructions. One embodiment of a processor comprises: a plurality of cores; an interconnect coupling the plurality of cores; and offload circuitry to transfer work from a first core of the plurality of cores to a second core of the plurality of cores without operating system (OS) intervention, the work comprising a plurality of instructions; the second core comprising a translator to translate information associated with a first instruction of the plurality of instructions from a first format usable on the first core to a second format usable on the second core; fetch, decode, and execution circuitry of the second core to fetch, decode, and/or execute the first instruction using the second format.
1. A processor comprising:
a plurality of cores;
an interconnect coupling the plurality of cores; and
offload circuitry to transfer work from a first core of the plurality of cores to a second core of the plurality of cores without operating system (OS) intervention, the work comprising a plurality of instructions, wherein the transfer comprises transmitting an offload start instruction to the second core, and wherein the offload start instruction is to identify an address to be accessed by the second core to perform the work;
the second core comprising a translator to translate information associated with a first instruction of the plurality of instructions from a first format usable on the first core to a second format usable on the second core, wherein the translator is to modify the address using an offset value to generate an updated address to be accessed by the second core;
fetch, decode, and execution circuitry of the second core to fetch, decode, and/or execute the first instruction using the second format.
2. The processor of claim 1 wherein the information comprises an address to be used when fetching, decoding, and/or executing the first instruction.
3. The processor of claim 1 wherein the first instruction comprises a Jump instruction.
4. The processor of claim 3 wherein the Jump instruction comprises a conditional jump with a first address to a jump code sequence when executed on the first core, wherein the translator is to translate the first address to a second address to identify the jump code sequence when executed on the second core.
5. The processor of claim 1 wherein the information comprises portions of context data required to execute the first instruction on the second core.
6. The processor of claim 1 wherein responsive to completing the offload work, the second core is to transmit an offload end message to the first core and to store results to memory.
7. The processor of claim 6 wherein the offload end message includes a second address pointer to identify a second memory location to be accessed by the first core to access the results.
8. A method comprising:
transferring work from a first core of a plurality of cores to a second core of the plurality of cores across an inter-core interconnect and without operating system (OS) intervention, the work comprising a plurality of instructions, wherein the transfer comprises transmitting an offload start instruction to the second core, and wherein the offload start instruction is to identify an address to be accessed by the second core to perform the work;
the second core comprising a translator to translate information associated with a first instruction of the plurality of instructions from a first format usable on the first core to a second format usable on the second core, wherein the translator is to modify the address using an offset value to generate an updated address to be accessed by the second core; and
fetching, decoding, and/or executing the first instruction using the second format.
9. The method of claim 8 wherein the information comprises an address to be used when fetching, decoding, and/or executing the first instruction.
10. The method of claim 8 wherein the first instruction comprises a Jump instruction.
11. The method of claim 10 wherein the Jump instruction comprises a conditional jump with a first address to a jump code sequence when executed on the first core, wherein the translator is to translate the first address to a second address to identify the jump code sequence when executed on the second core.
12. The method of claim 10 wherein the information comprises portions of context data required to execute the first instruction on the second core.
13. The method of claim 8 wherein responsive to completing the offload work, the second core is to transmit an offload end message to the first core and to store results to memory.
14. The method of claim 13 wherein the offload end message includes a second address pointer to identify a second memory location to be accessed by the first core to access the results.
15. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
transferring work from a first core of a plurality of cores to a second core of the plurality of cores across an inter-core interconnect and without operating system (OS) intervention, the work comprising a plurality of instructions, wherein the transfer comprises transmitting an offload start instruction to the second core, and wherein the offload start instruction is to identify an address to be accessed by the second core to perform the work;
the second core comprising a translator to translate information associated with a first instruction of the plurality of instructions from a first format usable on the first core to a second format usable on the second core, wherein the translator is to modify the address using an offset value to generate an updated address to be accessed by the second core; and
fetching, decoding, and/or executing the first instruction using the second format.
16. The non-transitory machine-readable medium of claim 15 wherein the information comprises an address to be used when fetching, decoding, and/or executing the first instruction.
17. The non-transitory machine-readable medium of claim 15 wherein the first instruction comprises a Jump instruction.
18. The non-transitory machine-readable medium of claim 17 wherein the Jump instruction comprises a conditional jump with a first address to a jump code sequence when executed on the first core, wherein the translator is to translate the first address to a second address to identify the jump code sequence when executed on the second core.
19. The non-transitory machine-readable medium of claim 18 wherein the information comprises portions of context data required to execute the first instruction on the second core.
20. The non-transitory machine-readable medium of claim 15 wherein responsive to completing the offload work, the second core is to transmit an offload end message to the first core and to store results to memory.
21. The non-transitory machine-readable medium of claim 20 wherein the offload end message includes a second address pointer to identify a second memory location to be accessed by the first core to access the results.