Compact magnetic storage memory cell
A memory comprising an array of memory cells, each memory cell comprising: first and second resistive storage elements each having at least first and second terminals; and a first transistor having: a first main conducting node connected to the first terminal of the first resistive element and to a first column/row line of the array; and a second main conducting node connected to the first terminal of the second resistive element and to a second column/row line of the array.
1. A memory comprising an array of memory cells, each memory cell comprising:
first and second resistive storage elements each having at least first and second terminals; and
a first transistor having:
a first main conducting node connected to the first terminal of the first resistive element and to a first column/row line of the array; and
a second main conducting node connected to the first terminal of the second resistive element and to a second column/row line of the array; and
a switch circuit comprising:
a first switch configured to be capable of coupling together the first and second terminals of the first resistive storage element of each memory cell of a first row or column of the array; and
a second switch configured to be capable of coupling together the first and second terminals of the second resistive storage element of each memory cell of the first row or column of the array.
2. The memory of claim 1 , wherein the first transistor further comprises a gate node connected to a third column/row line of the array.
3. The memory of claim 1 , wherein:
the second terminal of the first resistive element is connected to a fourth column/row line of the array; and
the second terminal of the second resistive element is connected to a fifth column/row line of the array.
4. The memory of claim 3 , wherein the first resistive storage element is configured to be programmable to have a high or low resistive state as a function of the direction of a write current driven through its first and second terminals.
5. The memory of claim 3 , wherein the second resistive storage element further comprises a third terminal and is configured to be programmable to have a high or low resistive state as a function of the direction of a write current driven through its second and third terminals.
6. The memory of claim 5 , wherein each memory cell further comprises a second transistor coupling the third terminal of the second resistive storage element to the fourth column/row line.
7. The memory of claim 3 , wherein the second resistive element is configured to be programmable to have a high or low resistive state as a function of the direction of a write current driven through its first and second terminals.
8. The memory of claim 3 , wherein the first and second resistive elements each comprise a third terminal and are configured to be programmable to have a high or low resistive state as a function of the direction of a write current driven through its second and third terminals.
9. The memory of claim 1 , wherein each memory cell further comprises:
a third resistive storage element having first and second terminals; and
a third transistor having:
a first main conducting node connected to the second terminal of the first resistive storage element; and
a second main conducting node connected to the first terminal of the third resistive storage element and to a sixth column/row line of the array.
10. The memory of claim 1 , wherein at least one of the first and second resistive storage elements is a magnetic storage element.
11. The memory of claim 1 , wherein at least one of the first and second resistive storage elements is one of:
a spin transfer torque (STT) element with in-plane anisotropy;
a spin transfer torque element with perpendicular-to-plane anisotropy;
a spin orbit torque magnetic tunnel junction (SOT-MTJ);
a metal oxide RAM (OxRAM) element;
a phase change RAM (PCRAM) element;
a phase change RAM (PCRAM) element;
a ferroelectric RAM (FeRAM) element; and
a conductive bridging RAM (CBRAM) element.
12. A method of accessing a memory cell of an array, each memory cell having first and second resistive storage elements each having first and second terminals, and a first transistor coupling together first terminals of the first and second resistive storage elements, the method comprising:
bypassing, using a switch circuit, one of the first and second resistive storage elements via column/row lines of the memory array in order to access the other of the first and second resistive storage elements, the switch circuit comprising:
a first switch configured to be capable of coupling together the first and second terminals of the first resistive storage element of each memory cell of a first row or column of the array; and
a second switch configured to be capable of coupling together the first and second terminals of the second resistive storage element of each memory cell of the first row or column of the array.
13. The method of claim 12 , further comprising:
applying a first voltage to a fourth column/row line of the array connected to the second terminal of the first resistive element; and
applying a second voltage to a fifth column/row line of the array connected to the second terminal of the second resistive element.