Memory circuit having resistive device coupled with supply voltage line

1. A memory circuit, comprising:

a first column of memory cells arranged along a first direction, each memory cell of the first column including a first supply segment;

a first supply voltage line extending along the first direction in a first conductive layer, the first supply voltage line being comprised of at least the first supply segments of the first column;

a second supply voltage line;

a first resistive device electrically connecting the first and second supply voltage lines, the first resistive device being located in a via layer;

a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and

a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.

2. The memory circuit of claim 1 , wherein:

the first material includes Tungsten or Cobalt.

3. The memory circuit of claim 1 , wherein the second supply voltage line extends along a second direction, different from the first direction, in a second conductive layer.

4. The memory circuit of claim 3 , wherein:

the first column of memory cells has a first end and a second end;

the second supply voltage line is disposed closer to the first end than the second end; and

the first resistive device is disposed closer to the first end than the second end.

5. The memory circuit of claim 3 , wherein:

the first resistive device represents a second type of via plug in the via layer; and

the via layer is formed between the first conductive layer and the second conductive layer.

6. The memory circuit of claim 3 , further comprising:

a second column of memory cells arranged along the first direction, each memory cell of the second column of memory cells including a second supply segment;

a third supply voltage line extending along the first direction in the first conductive layer, the third supply voltage line being made of at least the second supply segments of the second column of memory cells; and

a second resistive device electrically connecting the third supply voltage line and the second supply voltage line.

7. The memory circuit of claim 1 , wherein:

the second supply voltage line extends along the first direction in the first conductive layer; and

the via layer is adjacent to the first conductive layer.

8. The memory circuit of claim 1 , wherein:

relative to the first direction, a length of the first resistive device is greater than a length of the first type of via plug.

9. The memory circuit of claim 1 , wherein

a resistance value of the first resistive device is greater than the first type of via plug.

10. A memory circuit, comprising:

a column of memory cells arranged along a first direction, each memory cell including a first supply segment;

a first supply voltage line extending along the first direction in a first conductive layer, the first supply voltage line being comprised of at least the first supply segments;

a second supply voltage line extending along a second direction different from the first direction in a second conductive layer; and

a first resistive device in a via layer and electrically connecting the first and second supply voltage lines, the second supply voltage line being electrically coupled with the first supply voltage line through one or more conductive paths;

the first resistive device being in a lowest resistance path of the one or more conductive paths; and

relative to the first direction, a length of the first resistive device being greater than a length of a via plug in the via layer.

11. The memory circuit of claim 10 , wherein:

the first resistive device is formed of a material including Tungsten or Cobalt.

12. The memory circuit of claim 10 , wherein:

the column of memory cells has a first end and a second end;

the second supply voltage line is disposed closer to the first end than the second end;

the first resistive device is disposed closer to the first end than the second end; and

the memory circuit further comprises:

a third supply voltage line extending along the second direction in the second conductive layer, the third supply voltage line being disposed closer to the second end than the first end; and

a second resistive device electrically connecting the first supply voltage line and the third supply voltage line, the second resistive device is disposed closer to the second end than the first end.

13. The memory circuit of claim 10 , further comprising:

a supply voltage source electrically coupled with first supply voltage line through the second supply voltage line and the first resistive device.

14. The memory circuit of claim 10 , wherein:

a resistance value of the first resistive device is greater than the via plug.

15. The memory circuit of claim 10 , wherein:

the first resistive device is formed of a first material;

the via plug is formed of a second material; and

the first material is different than the second material.

16. The memory circuit of claim 10 , wherein:

the length, L, of the first resistive device is in a range as follows:

(≈50 nm)≤ L ≤(≈150 nm).

17. A memory circuit, comprising:

a column of memory cells arranged along a first direction, each memory cell including a first supply segment;

a first supply voltage line extending along the first direction in a first conductive layer, the first supply voltage line being comprised of at least the first supply segments;

a second supply voltage line extending along a second direction different from the first direction in a second conductive layer; and

a first resistive device in a via layer and electrically connecting the first and second supply voltage lines, the second supply voltage line being electrically coupled with the first supply voltage line through one or more conductive paths;

the first resistive device being in a lowest resistance path of the one or more conductive paths; and

the first resistive device being a well resistor.

18. The memory circuit of claim 17 , wherein:

the column of memory cells has a first end and a second end;

the second supply voltage line is disposed closer to the first end than the second end; and

the first resistive device is disposed closer to the first end than the second end.

19. The memory circuit of claim 17 , wherein:

the first resistive device has a resistance, R, in a range as follows:

(≈1.0 kΩ)≤ R ≤(≈1.0 kΩ).

20. The memory circuit of claim 17 , wherein:

the first resistive device is formed of a first material;

the first supply voltage line is formed of a second material; and

the first material has a different resistivity than the second material.