IP Library Granted Patent US 10,826,471
Granted Patent B2
US 10,826,471 · App. 16/460,140 · Granted Nov 3, 2020

Switch mode power supply with ramp generator for wide frequency range pulse width modulator or the like

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Quick Facts
Patent No.
US 10,826,471
App. No.
16/460,140
Granted
Nov 3, 2020
Kind
B2
Abstract

A switch mode power supply includes an error amplifier, an oscillator, a pulse width modulation logic circuit, and an output stage. The oscillator includes a current generator that receives a clock signal and provides a current proportional to a frequency of the clock signal, a current mirror having an input coupled to the output of the current generator, and a first capacitor having a first terminal coupled to an output of the current mirror and providing a ramp signal, and a second terminal coupled to power supply voltage terminal. The pulse width modulation logic circuit compares the output of the error amplifier with the ramp signal, and generates a high- and low-side drive signals respectively to first and second outputs in response to the comparing. The output stage is responsive to the high- and low-side drive signals for alternatively coupling a switch terminal between an input voltage terminal and ground.

Claims (57)

1. A switch mode power supply, comprising:

an error amplifier having a first input for receiving a first reference voltage, a second input for receiving a feedback signal, and an output;

an oscillator comprising:

a current generator having an input for receiving a clock signal, and an output for providing a current proportional to a frequency of said clock signal;

a current mirror having an input coupled to said output of said current generator, and an output; and

a first capacitor having a first terminal coupled to said output of said current mirror and providing a ramp signal, and a second terminal coupled to a first power supply voltage terminal,

a pulse width modulation logic circuit for comparing said output of said error amplifier with said ramp signal, and generating a high-side drive signal and a low-side drive signal respectively to first and second outputs in response to said comparing; and

an output stage coupled to said first and second outputs of said pulse width modulation logic circuit and responsive to said high-side drive signal and said low-side drive signal for alternatively coupling a switch terminal between an input voltage terminal and a ground voltage terminal, respectively.

2. The switch mode power supply of claim 1 , wherein said current generator comprises:

a first transistor having a first current electrode for providing said current, a second current electrode, and a control electrode;

an amplifier having a non-inverting input for receiving a second reference voltage, an inverting input coupled to said second current electrode of said first transistor, and an output coupled to said control electrode of said first transistor; and

a variable resistor having a first terminal coupled to said second current electrode of said first transistor, a second terminal coupled to said first power supply voltage terminal, and a control terminal for receiving said clock signal.

3. The switch mode power supply of claim 2 , wherein said variable resistor comprises a switched capacitor resistor.

4. The switch mode power supply of claim 3 , wherein said variable resistor comprises:

a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving a complement of said clock signal, and a second current electrode;

a second capacitor having a first terminal coupled to said second current electrode of said second transistor, and a second terminal coupled to said first power supply voltage terminal; and

a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving said clock signal, and a second current electrode coupled to said first power supply voltage terminal.

5. The switch mode power supply of claim 4 , further comprising:

a clock circuit having a first output for providing said clock signal, a second output for providing said complement of said clock signal, and a third output for providing a divided clock signal; and

a fourth transistor having a first current electrode coupled to said first terminal of said first capacitor, a control electrode coupled to said third output of said clock circuit, and a second current electrode coupled to said first power supply voltage terminal.

6. The switch mode power supply of claim 5 , wherein said pulse width modulation logic circuit further operates in synchronism with said divided clock signal.

7. The switch mode power supply of claim 5 , further comprising:

a narrow pulse generator coupled between said third output of said clock circuit and said control electrode of said fourth transistor and responsive to said divided clock signal for providing a narrow clock pulse to said control electrode of said fourth transistor wherein said narrow clock pulse has a rising edge aligned with a rising edge of said divided clock signal, and an active period less than an active period of said divided clock signal.

8. The switch mode power supply of claim 2 , further comprising:

a first current source having a first terminal coupled to said second current electrode of said first transistor, and a second terminal coupled to said first power supply voltage terminal; and

a second current source having a first terminal coupled to said first terminal of said first capacitor, and a second terminal coupled to said first power supply voltage terminal.

9. The switch mode power supply of claim 2 , further comprising:

a first resistor having a first terminal for receiving an input voltage, and a second terminal coupled to said non-inverting input of said amplifier for providing said reference voltage; and

a second resistor having a first terminal coupled to said second terminal of said first resistor, and a second terminal coupled to said first power supply voltage terminal.

10. The switch mode power supply of claim 2 , wherein said current mirror comprises:

a fifth transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to said control electrode thereof and to said first current electrode of said first transistor; and

a sixth transistor having a first current electrode coupled to said second power supply voltage terminal, a control electrode coupled to said second current electrode of said fifth transistor, and a second current electrode coupled to said first terminal of said first capacitor.

11. The switch mode power supply of claim 10 , wherein said second current electrode of said fifth transistor is coupled to said control electrode of said sixth transistor through a direct current (DC) filter.

12. The switch mode power supply of claim 1 , wherein said error amplifier, said oscillator, said pulse width modulation logic circuit, and said output stage are combined on a single integrated circuit chip.

13. A method comprising:

setting a value of a variable resistor according to a frequency of a first clock signal;

generating an input current according to said value of said variable resistor;

mirroring said input current to form a ramp current proportional to said input current; and

alternately charging a first capacitor using said ramp current and discharging said first capacitor in synchronism with a second clock signal;

forming a ramp signal from a voltage on said first capacitor; and

using said ramp signal to form an output voltage in a switch mode power supply.

14. The method of claim 13 wherein said setting said value of said variable resistor comprises:

switching a first terminal of a second capacitor to a first terminal of said variable resistor in response to a complement of said first clock signal; and

switching said first terminal of said second capacitor to a power supply voltage terminal in response to said first clock signal.

15. The method of claim 14 , further comprising:

discharging said first capacitor in synchronism with a divided clock signal formed by dividing said first clock signal.

16. The method of claim 13 wherein said generating said input current comprises:

providing said input current from a first current electrode of a first transistor; and

biasing a control electrode of said first transistor according to a difference between a reference voltage and a voltage on a second current electrode of said first transistor.

17. The method of claim 16 , further comprising:

forming said reference voltage as a proportion of an input voltage.

18. The method of claim 13 , wherein using said ramp signal to form said output voltage in said switch mode power supply comprises:

pulse width modulating a conduction time of a first transistor to switch current from an input voltage to an inductor in response to said ramp signal.

19. The method of claim 18 , wherein said pulse width modulating comprises:

pulse width modulating said conduction time of said first transistor to switch current to said inductor in response to both said ramp signal and a feedback signal derived from said output voltage.

20. The method of claim 18 , wherein using said ramp signal to form said output voltage in said switch mode power supply further comprises:

pulse width modulating a conduction time of a second transistor to switch current from said inductor to a ground voltage in response to said ramp signal.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 051145, FRAME 0062 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064079/0474 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXCLUSION OF FAIRCHILD SEMICONDUCTOR CORPORATION OF CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 051145 FRAME 0062. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Dec 3, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051170/0781 →
SECURITY INTEREST Recorded Nov 26, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051145/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2019
From: ZHU, HUA; YAO, KAIWEI
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 049654/0577 →