Image sensors with reduced signal sampling kickback
An image sensor may include an array of image pixels. The image pixel pixels may be arranged in columns and rows. Each column of image pixels may be coupled to column readout circuitry via respective column lines. The column readout circuitry may include amplifier circuitry, a first source follower stage, and a second source follower stage. The first and second source follower stages may be interposed between the amplifier circuitry and a sampling capacitor. A switch may be interposed between the first and second source follower stages. The second source follower transistor may be configured to provide an intermediate sampling voltage to the sampling capacitor. The first source follower transistor may be configured to provide a final sampling voltage to the sampling capacitor. In such a manner, kickback from sampling signals using readout circuitry may be reduced.
1. An image sensor comprising:
an image pixel; and
readout circuitry coupled to the image pixel and configured to sample a signal from the image pixel, the readout circuitry comprising:
amplifier circuitry;
a first source follower stage;
a second source follower stage;
a charge storage structure configured to store a voltage associated with the sampled signal, wherein the first and second source follower stages are coupled between the amplifier circuitry and the charge storage structure; and
a switch that couples the first source follower stage to the charge storage structure.
2. The image sensor defined in claim 1 , wherein the amplifier circuitry comprises an output terminal, and wherein the output terminal is coupled to the first source follower stage and is coupled to the second source follower stage.
3. The image sensor defined in claim 2 , wherein the first source follower stage comprises a set of transistors connected in series between first and second supply terminals.
4. The image sensor defined in claim 3 , wherein the second source follower stage comprises an additional set of transistors connected in series between third and fourth supply terminals.
5. The image sensor defined in claim 4 , wherein a first transistor in the set of transistors has a gate terminal coupled to the output terminal of the amplifier circuitry, and wherein a second transistor in the additional set of transistors has a gate terminal coupled to the output terminal of the amplifier circuitry.
6. The image sensor defined in claim 1 , wherein
the switch couples the first source follower stage to the second source follower stage.
7. The image sensor defined in claim 1 , wherein the readout circuitry comprises:
an additional switch that couples the second source follower stage to the charge storage structure.
8. The image sensor defined in claim 7 , wherein the readout circuitry comprises:
a biasing circuit configured to provide a bias voltage to the charge storage structure through the additional switch.
9. The image sensor defined in claim 1 , wherein the amplifier circuitry comprises an input terminal coupled to a column line connected to the image pixel and an output terminal coupled to a gate terminal of a first transistor in the first source follower stage.
10. The image sensor defined in claim 9 , wherein the first source follower stage includes second and third transistors coupled in series with the first transistor, and a common source-drain terminal of the second and third transistors is coupled to the input terminal of the amplifier circuitry.
11. The image sensor defined in claim 10 , wherein the second source follower stage includes fourth and fifth transistors coupled in series, and a common source-drain terminal of the fourth and fifth transistors is coupled to the common source-drain terminal of the second and third transistors.
12. A method of operating readout circuitry coupled to an image sensor pixel using a column line, the method comprising:
with amplifier circuitry in the readout circuitry, receiving a signal from the image sensor pixel using the column line;
with a source follower stage coupled to the amplifier circuitry, providing an intermediate sampling voltage associated with the signal to a sampling voltage terminal by activating a switch coupled between the source follower stage and the sampling voltage terminal; and
with an additional source follower stage coupled to the amplifier circuitry, providing a final sampling voltage associated with the signal to the sampling voltage terminal after providing the intermediate sampling voltage with the source follower stage.
13. The method defined in claim 12 , further comprising:
enabling a biasing circuit to provide a reset voltage to the sampling voltage terminal.
14. The method defined in claim 12 , further comprising:
while the switch is activated, activating the source follower stage by asserting at least one control signal for at least one transistor in the source follower stage.
15. The method defined in claim 12 , wherein providing the final sampling voltage associated with the signal to the sampling voltage terminal comprises activating the switch.
16. An imaging system comprising:
processing circuitry;
an image sensor pixel array; and
column readout circuitry coupled to the image sensor pixel array via at least one column line, wherein the column readout circuitry comprises:
a charge storage structure operable to store signals sampled from the column line;
a biasing circuit operable to provide a bias voltage to the charge storage structure;
a set of transistors coupled in series and operable to provide a coarse sampling voltage to the charge storage structure; and
an additional set of transistors coupled in series and operable to provide a final sampling voltage to the charge storage structure.
17. The imaging system defined in claim 16 , wherein the column readout circuitry comprises:
a switching circuit interposed between the set of transistors and the additional set of transistors, wherein the additional set of transistors is operable to provide the final sampling voltage through the switching circuit.
18. The imaging system defined in claim 17 , wherein the column readout circuitry comprises:
an additional switching circuit interposed between the additional set of transistors and the charge storage structure, wherein the biasing circuit is operable to provide the bias voltage through the additional switching circuit, wherein the set of transistors is operable to provide the coarse sampling voltage through the additional switching circuit, and wherein the additional set of transistors is operable to provide the final sampling voltage through the additional switching circuit.
19. The imaging system defined in claim 18 , wherein the column readout circuitry comprises:
an amplifier having an output terminal coupled to a gate terminal of a first transistor in the set of transistors and coupled to a gate terminal of a second transistor in the additional set of transistors.
20. The imaging system defined in claim 16 , wherein the set of transistors is coupled between a positive supply terminal and a ground supply terminal, and wherein the additional set of transistors is coupled between an additional positive supply terminal and an additional ground supply terminal.