Display panel and method of manufacturing the same
View Patent ↗A display panel includes a substrate and a first layer of wires. The first layer of wires are disposed on the substrate. A lower portion of the first layer of wires includes a first high attachment metal layer, an upper portion of the first layer of wires includes a second high attachment metal layer, and a middle of the first layer of wires includes an intermediate electroconductive layer. The first layer of wires are connected to a column scan driver of the display panel.
1. A display panel, comprising:
a substrate; and
a first layer of wires disposed on the substrate, wherein a lower portion of the first layer of wires comprises a first high attachment metal layer, an upper portion of the first layer of wires comprises a second high attachment metal layer, a middle of the first layer of wires comprises an intermediate electroconductive layer, and the first layer of wires are connected to a column scan driver of the display panel,
wherein the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor; and the first layer of wires are disposed with the second high attachment metal layer only on the wire segment of the gate.
2. The display panel according to claim 1 , wherein a thickness of the intermediate electroconductive layer is greater than a thickness of the first high attachment metal layer and a thickness of the second high attachment metal layer.
3. The display panel according to claim 1 , wherein a width of a bottom portion of the intermediate electroconductive layer is greater than a width of a top portion of the intermediate electroconductive layer, a width of the first high attachment metal layer is the same as the width of the bottom portion of the intermediate electroconductive layer, and a width of the second high attachment metal layer is the same as the width of the top portion of the intermediate electroconductive layer.
4. The display panel according to claim 1 , wherein the intermediate electroconductive layer is made of copper, aluminum, silver, gold, chromium, molybdenum, or any of their alloys.
5. The display panel according to claim 1 , wherein the first high attachment metal layer and the second high attachment metal layer are made of molybdenum or a molybdenum alloy.
6. The display panel according to claim 1 , wherein an insulating layer is disposed on the wire segment of the gate, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of a thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.
7. The display panel according to claim 1 , wherein the first layer of wires are integrally covered with the first high attachment metal layer and the second high attachment metal layer, an insulating layer is disposed on the first layer of wires, the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.
8. A method of manufacturing a display panel, comprising steps of:
disposing a first high attachment metal layer on a substrate;
disposing an intermediate electroconductive layer on the first high attachment metal layer;
disposing a second high attachment metal layer on the intermediate electroconductive layer; and
etching the first high attachment metal layer, the intermediate electroconductive layer and the second high attachment metal layer to form a first layer of wires,
wherein the intermediate electroconductive layer is etched to have a top portion and a bottom portion wider than the top portion, the first high attachment metal layer is etched to have a width the same as a width of the bottom portion of the intermediate electroconductive layer, and the second high attachment metal layer is etched to have a width the same as a width of the top portion of the intermediate electroconductive layer,
wherein the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor, and the first layer of wires are disposed with the second attachment metal layer only on the wire segment of the gate.
9. The method according to claim 8 , wherein the intermediate electroconductive layer is made of copper, aluminum, silver, gold, chromium, molybdenum, or any of their alloys.
10. The method according to claim 8 , wherein the first high attachment metal layer and the second high attachment metal layer are made of molybdenum or a molybdenum alloy.
11. The method according to claim 8 , wherein an insulating layer is disposed on the wire segment of the gate, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.
12. The method according to claim 8 , wherein the first layer of wires are integrally covered with the first high attachment metal layer and the second high attachment metal layer, an insulating layer is disposed on the first layer of wires, the first layer of wires comprise a wire segment of a gate disposed on a thin film transistor, a semiconductor layer corresponding to the wire segment of the gate is disposed on the insulating layer, a source and a drain of the thin film transistor separated from each other are disposed on two ends of the semiconductor layer, a trench is disposed between the source and the drain, and a bottom portion of the trench is the semiconductor layer.