Two-terminal vertical 1T-DRAM and method of fabricating the same

1. A two-terminal vertical 1T-DRAM, comprising:

a cathode layer formed of a first-type high-concentration semiconductor layer;

a base region comprising a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and

an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer,

wherein a doping concentration of the base region increases from 1×10 16 cm −3 to 1×10 17 cm −3 or from 1×10 18 cm −3 to 1×10 19 cm −3 depending on an amount of impurities to be added, and

wherein, when a doping concentration of the base region increases from 1×10 18 cm −3 to 1×10 19 cm −3 , the base region generates latch-up and increases a latch-up voltage, and a state of the base region is determined as “high” according to increase in the latch-up voltage.

2. The two-terminal vertical 1T-DRAM according to claim 1 , wherein

the first-type high-concentration semiconductor layer comprises one of an n + -type semiconductor layer and a p + -type semiconductor layer; and

the second-type high-concentration semiconductor layer comprises the other of the n + -type semiconductor layer and the p + -type semiconductor layer.

3. The two-terminal vertical 1T-DRAM according to claim 2 , wherein the first-type high-concentration semiconductor layer is an n+-type semiconductor layer, and the second-type high-concentration semiconductor layer is a p+-type semiconductor layer.

4. The two-terminal vertical 1T-DRAM according to claim 2 , wherein the first-type high-concentration semiconductor layer is the p+-type semiconductor layer, and the second-type high-concentration semiconductor layer is the n+-type semiconductor layer.

5. The two-terminal vertical 1T-DRAM according to claim 1 , wherein

the first-type low-concentration semiconductor layer comprises one of a p-type semiconductor layer and an n-type semiconductor layer; and

the second-type low-concentration semiconductor layer comprises the other of the p-type semiconductor layer and the n-type semiconductor layer.

6. The two-terminal vertical 1T-DRAM according to claim 5 , wherein the first-type low-concentration semiconductor layer is a p-type semiconductor layer, and the second-type low-concentration semiconductor layer is an n-type semiconductor layer.

7. The two-terminal vertical 1T-DRAM according to claim 5 , wherein the first-type low-concentration semiconductor layer is the n-type semiconductor layer, and the second-type low-concentration semiconductor layer is the p-type semiconductor layer.

8. The two-terminal vertical 1T-DRAM according to claim 1 , wherein, when the doping concentration of the base region increases from 1×10 16 cm −3 to 1×10 17 cm −3 , state of the base region is determined as “low”.

9. The two-terminal vertical 1T-DRAM according to claim 1 , wherein a concentration of ions for forming the second-type high-concentration semiconductor layer is set to 1×10 20 cm −3 , and the ions are injected to form the anode layer.

10. The two-terminal vertical 1T-DRAM according to claim 1 , wherein the first-type low-concentration semiconductor layer and the second-type low-concentration semiconductor layer are each formed to have a thickness of 80 nm or more.

11. A two-terminal vertical 1T-DRAM, comprising:

a cathode layer formed of a first-type high-concentration semiconductor layer;

a base region comprising a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and

an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer,

wherein a concentration of ions for forming the first-type high-concentration semiconductor layer is set to 1×10 20 cm −3 , and the ions are injected to form the cathode layer.

12. A method of fabricating a two-terminal vertical 1T-DRAM, comprising:

a step of forming a cathode layer formed of a first-type high-concentration semiconductor layer;

a step of forming a base region comprising a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and

a step of forming an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer,

wherein the step of forming the base region comprises a step of adjusting a doping concentration of the base region so that the doping concentration of the base region increases from 1×10 16 cm −3 to 1×10 17 cm −3 or from 1×10 18 cm −3 to 1×10 19 cm −3 depending on an amount of impurities to be added, and

wherein the step of adjusting the doping concentration of the base region so that the doping concentration of the base region increases from 1×10 18 cm −3 to 1×10 19 cm −3 comprises a step of generating latch-up according to increase in the doping concentration of the base region and increasing a latch-up voltage; and

a step of determining a state of the base region as “high” according to increase in the latch-up voltage.

13. The method according to claim 12 , wherein the step of adjusting the doping concentration of the base region so that the doping concentration of the base region increases from 1×10 16 cm −3 to 1×10 17 cm −3 comprises a step of determining the state of the base region as “low” according to increase in the doping concentration of the base region.

14. The method according to claim 12 , wherein the first-type low-concentration semiconductor layer and the second-type low-concentration semiconductor layer are each formed to have a thickness of 80 nm or more.