Hardened plug for improved shorting margin
In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.
1. An integrated circuit structure, comprising:
a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect;
a second layer having a third conductive interconnect;
a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect;
a plug between the first layer and second layer, wherein the plug is laterally adjacent to the conductive via and between at least a portion of the via and the first conductive interconnect;
a hardmask material above the dielectric; and
wells above the conductive interconnects.
2. The integrated circuit structure of claim 1 , wherein the wells are filled with the dielectric.
3. The integrated circuit structure of claim 1 , wherein a well above the first conductive interconnect is filled with the hardmask material.
4. The integrated circuit structure of claim 3 , wherein the hardmask material is a first hardmask material, and a well above the second conductive interconnect is filled with a second hardmask material different from the first hardmask material.
5. The integrated circuit structure of claim 1 , wherein the plug comprises silicon and carbon.
6. The integrated circuit structure of claim 1 , wherein the plug comprises a metal oxide.
7. The integrated circuit structure of claim 1 , wherein the plug comprises a thin film.
8. An integrated circuit die, comprising:
a solid-state structure, comprising:
a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect;
a second layer having a third conductive interconnect;
a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect;
a hardmask material between the first layer and the second layer;
a plug between the hardmask material and the conductive via, wherein the plug includes a dielectric material having a material composition different from that of the hardmask material; and
wells above the conductive interconnects.
9. The integrated circuit die of claim 8 , wherein the wells have the dielectric therein.
10. The integrated circuit die of claim 8 , wherein a well above the first conductive interconnect is filled with the hardmask material.
11. The integrated circuit die of claim 10 , wherein the hardmask material is a first hardmask material, a well above the second conductive interconnect has a second hardmask material therein, and the second hardmask material is different from the first hardmask material.
12. The integrated circuit die of claim 8 , wherein the plug comprises silicon and carbon.
13. The integrated circuit die of claim 8 , wherein the plug comprises a metal and oxygen.
14. The integrated circuit die of claim 8 , wherein the plug comprises a thin film.
15. A system on a chip, comprising:
a solid-state structure, comprising:
a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect;
a second layer having a third conductive interconnect;
a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect;
a plug between the first layer and second layer to prevent the via from electrically shorting to the first conductive interconnect;
a hardmask material above the dielectric; and
wells above the conductive interconnects.
16. The system on a chip of claim 15 , wherein the wells are filled with the dielectric, or a well above the first conductive interconnect is filled with the hardmask material.
17. The system on a chip of claim 15 , wherein the plug comprises silicon and carbon.
18. The system on a chip of claim 15 , wherein the plug comprises a metal and oxygen.