IP Library Granted Patent US 11,830,848
Granted Patent B2
US 11,830,848 · App. 16/467,975 · Granted Nov 28, 2023

Electronic device package

Inventors: Zhicheng Ding (Shanghai, CN); Bin Liu (Shanghai, CN); Yong She (Songjiang, CN); Hyoung Il Kim (Folsom, CA)
Assignee: Intel Corporation
H01L25/0652H01L21/568H01L23/3128H01L23/49811H01L23/5383H01L25/0657H01L25/50H01L2225/0651H01L2225/06506H01L2225/06562
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Quick Facts
Patent No.
US 11,830,848
App. No.
16/467,975
Granted
Nov 28, 2023
Kind
B2
Abstract

Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

Claims (19)

1. An electronic device package, comprising:

an electronic component;

a redistribution layer;

an interposer on the redistribution layer and laterally spaced apart from the electronic component, the interposer electrically coupling the redistribution layer and the electronic component, the interposer having interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer, and the interposer having a first outermost sidewall and a second outermost sidewall between the top side and the bottom side, the second outermost sidewall laterally opposite the first outermost sidewall, wherein a density of the interconnect interfaces on the top side is greater than a density of the interconnect interfaces on the bottom side, and wherein the redistribution layer extends laterally beyond the first outermost sidewall and the second outermost sidewall of the interposer; and

a mold compound encapsulating the electronic component and the interposer, the mold compound on the redistribution layer.

2. The electronic device package of claim 1 , wherein the interconnect interfaces on the top side of the interposer comprise wire bond landings.

3. The electronic device package of claim 2 , wherein the interposer and the electronic component are electrically coupled by a wire bond connection.

4. The electronic device package of claim 1 , wherein the interconnect interfaces on the bottom side of the interposer comprise pads.

5. The electronic device package of claim 1 , wherein the mold compound comprises an epoxy.

6. The electronic device package of claim 1 , wherein the redistribution layer comprises a single layer.

7. The electronic device package of claim 1 , wherein the electronic component comprises a plurality of electronic components in a stacked arrangement.

8. The electronic device package of claim 7 , wherein at least some of the plurality of electronic components are electrically coupled to one another by wire bond connections.

9. The electronic device package of claim 1 , further comprising a second electronic component, and a second interposer electrically coupling the redistribution layer and the second electronic component.

10. The electronic device package of claim 9 , wherein the second electronic component comprises a plurality of second electronic components in a stacked arrangement.

11. The electronic device package of claim 10 , wherein at least some of the plurality of second electronic components are electrically coupled to one another by wire bond connections.

12. The electronic device package of claim 1 , further comprising interconnect structures coupled to a bottom side of the redistribution layer to facilitate electrically coupling the electronic device package with an external electronic component.

13. The electronic device package of claim 12 , wherein the interconnect structures comprise solder balls.

14. The electronic device package of claim 1 , wherein the electronic component comprises an integrated circuit.

15. The electronic device package of claim 14 , wherein the integrated circuit comprises an application specific integrated circuit, computer memory, or a combination thereof.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072792/0414 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2023
From: DING, ZHICHENG; LIU, BIN; SHE, YONG; KIM, HYOUNG IL
To: INTEL CORPORATION
Reel/Frame 064559/0966 →
Continuity (1)
Related Publication 20210265305A1 · Aug 26, 2021