Array substrate, manufacturing method thereof, and organic light emitting diode display device

1. A manufacturing method of an array substrate, comprising:

forming a first thin film transistor including a first semiconductor pattern on a substrate, forming the first thin film transistor comprising forming a first electrode pattern including a first source electrode and a first drain electrode and a second electrode pattern including a first auxiliary source electrode and a first auxiliary drain electrode through two patterning processes, respectively;

forming a second thin film transistor on the substrate, forming the second thin film transistor comprising forming a second source electrode and a second drain electrode through one patterning process,

wherein the second electrode pattern, the second source electrode and the second drain electrode are formed in the same patterning process, the first electrode pattern is connected with the first semiconductor pattern, the first auxiliary source electrode is electrically connected with the first source electrode, and the first auxiliary drain electrode is electrically connected with the first drain electrode,

wherein forming the first thin film transistor further comprises: forming the first semiconductor pattern before forming the first source electrode and the first drain electrode; forming the second thin film transistor further comprises forming a second semiconductor pattern before forming the second source electrode and the second drain electrode, an orthogonal projection of the first semiconductor pattern on the substrate and an orthogonal projection of the second semiconductor pattern on the substrate do not overlap with each other,

wherein the material of the first semiconductor pattern is polysilicon and the material of the second semiconductor pattern is metal oxide,

the manufacturing method further comprises: before forming the first source electrode and the first drain electrode, forming a first insulating layer on the first semiconductor pattern; forming a first via hole in the first insulating layer to expose part of the first semiconductor pattern, and performing a high-temperature annealing on the exposed part of the first semiconductor pattern and/or removing an oxide layer on a surface of the first semiconductor pattern.

2. The manufacturing method of the array substrate according to claim 1 , wherein a sum of lengths of the first source electrode and the first auxiliary source electrode in a direction perpendicular to the substrate is greater than a length of the second source electrode in a direction perpendicular to the substrate, and/or

a sum of lengths of the first drain electrode and the first auxiliary drain electrode in the direction perpendicular to the substrate is greater than the length of the second drain electrode in the direction perpendicular to the substrate.

3. The manufacturing method of the array substrate according to claim 1 , wherein a material of the first semiconductor pattern is different from that of the second semiconductor pattern.

4. The manufacturing method of the array substrate according to claim 1 , wherein the substrate is a flexible substrate, and the manufacturing method further comprises: forming a barrier layer on the substrate before forming the first semiconductor pattern;

forming a first groove in the first insulating layer to expose the barrier layer simultaneously with forming the first via hole in the first insulating layer.

5. The manufacturing method of the array substrate according to claim 4 , wherein the method further comprises: before forming the first auxiliary source electrode and the first auxiliary drain electrode, forming a third insulating layer on the array substrate formed with the second metal pattern;

forming a second via hole and a third via hole in the third insulating layer and patterning the third insulating layer located in the first groove to form a second groove, wherein the first auxiliary source electrode and the first auxiliary drain electrode are respectively electrically connected with the first source electrode and the first drain electrode through the second via hole, the second source electrode and the second drain electrode are respectively electrically connected with the second semiconductor pattern through the third via hole, and forming the second groove comprises etching the third insulating layer and a partial thickness of the third insulating layer to expose the barrier layer; or forming the second groove includes etching the third insulating layer and the barrier layer to expose the substrate.

6. The manufacturing method of the array substrate according to claim 1 , wherein forming the first electrode pattern further comprises forming a first metal pattern.

7. The manufacturing method of the array substrate according to claim 6 , further comprising:

forming a laminated structure of a second insulating pattern and a second metal pattern on the first metal pattern and the second semiconductor pattern respectively by a patterning process on the array substrate formed with the second semiconductor pattern,

wherein the second insulating pattern is located on a side of the second metal pattern facing the substrate, and an orthogonal projection of the second metal pattern on the substrate overlaps with an orthogonal projection of the first metal pattern on the substrate, and a distance between the first metal pattern and the second metal pattern is 1000-1500 angstroms.

8. The manufacturing method of the array substrate according to claim 7 , wherein the method further comprises: simultaneously with forming the first auxiliary source electrode, the first auxiliary drain electrode, the second source electrode and the second drain electrode, forming a third metal pattern, wherein an orthographic projection of the third metal pattern on the substrate overlaps with an orthographic projection of the second metal pattern on the substrate.

9. The manufacturing method of the array substrate according to claim 8 , further comprising:

forming a fourth insulating layer on the array substrate formed with the third metal pattern;

patterning the fourth insulating layer to expose the first auxiliary source electrode, the first auxiliary drain electrode, and the second groove;

forming an organic film layer on the array substrate on which the fourth insulating layer is formed, the organic film layer filling the second groove;

forming a fourth via hole in the organic film layer to expose the first auxiliary source electrode and the first auxiliary drain electrode;

forming a fourth metal layer on the organic film layer;

patterning the fourth metal layer to form a fourth metal pattern, a second auxiliary source electrode and a second auxiliary drain electrode, wherein an orthogonal projection of the fourth metal pattern on the substrate overlaps with the orthogonal projection of the third metal pattern on the substrate, and the second auxiliary source electrode and the second auxiliary drain electrode are electrically connected with the first auxiliary source electrode and the first auxiliary drain electrode respectively through the fourth via hole.