Heterogeneous integration of components onto compact devices using moire based metrology and vacuum based pick-and-place

1. A method for assembling heterogeneous components onto a product substrate, the method comprising:

selectively picking a subset of elements from a source wafer by a vacuum superstrate attached to said subset of elements;

placing said selectively picked subset of elements onto an adhesive on said product substrate, wherein said placement is performed with a sub-100 nm placement precision onto said adhesive in a liquid state, wherein said adhesive is inkjetted or spin-coated onto said product substrate; and

securely attaching said selectively picked subset of elements onto said product substrate by holding onto said subset of elements using said vacuum superstrate until said adhesive reaches its gel point.

2. The method as recited in claim 1 , wherein said distribution is arbitrary.

3. The method as recited in claim 1 , wherein said subset of elements are selectively picked from said source wafer using pick-and place, wherein said pick-and-place is highly parallel.

4. The method as recited in claim 1 , wherein said elements are fabricated on source wafers with a buried sacrificial layer that is partially or fully removed using a bulk etch process.

5. The method as recited in claim 4 further comprising:

etching said buried sacrificial layer using an etchant, wherein said etchant comprises vapor hydrofluoric acid.

6. The method as recited in claim 5 , wherein said etching of said buried sacrificial layer using said etchant is timed in such a manner that pillar-like structures remain underneath said elements post-etch.

7. The method as recited in claim 4 further comprising:

bulk-releasing said subset of elements by etching off an underlying sacrificial layer while holding a vacuum.

8. The method as recited in claim 7 further comprising:

transferring said subset of elements to an intermediate glass substrate with an ultraviolet-detacking adhesive on said intermediate glass substrate.

9. The method as recited in claim 8 further comprising:

exposing an underside of an element to selective ultraviolet light to selectively release said element.

10. The method as recited in claim 1 , wherein said elements vary in size from sub-10 micrometers on a side to over 1 millimeter on a side.

11. The method as recited in claim 1 , wherein assembling of said subset of elements achieves sub-50 nm scale alignment capability.

12. The method as recited in claim 11 , wherein alignment between said vacuum superstrate and said product wafer is achieved using a moiré metrology scheme.

13. The method as recited in claim 12 further comprising:

performing coarse alignment using stage actuators as picked elements are brought to said product wafer;

performing fine alignment after said subset of elements are touching an uncured adhesive on said product wafer.

14. The method as recited in claim 1 , wherein said subset of elements are encapsulated in a chemically inert layer of a particular thickness to protect from chemical damage and to mitigate mechanical scratching using a subsequent material removal using a chemical mechanical polishing step.

15. The method as recited in claim 1 further comprising:

selectively picking said subset of elements using a vacuum based pickup mechanism comprising said vacuum substrate; and

selectively releasing said subset of elements using an etchant gas or a mechanical pulling approach.

16. The method as recited in claim 15 ,

wherein said adhesive is a single or a multi-component adhesive on said product wafer.

17. The method as recited in claim 16 , wherein said adhesive is cured using ultraviolet light until it reaches said gel point.

18. The method as recited in claim 17 further comprising:

implementing a subsequent vacuum deposition process to further secure said securely attached subset of elements.

19. The method as recited in claim 15 , wherein microelectromechanical systems (MEMS) based valves are used to selectively activate vacuum holes to enable said vacuum based pickup mechanism.

20. The method as recited in claim 15 , wherein a custom pickup layer is used for each specific pickup configuration of said subset of elements.

21. The method as recited in claim 1 , wherein said method is used for constructing Application Specific Integrated Circuits (ASICs) from feedstock circuits.

22. The method as recited in claim 21 further comprising:

picking up a feedstock from a maximally depleted feedstock source wafer at a beginning of product assembly;

picking up maximum possible feedstocks from a next most depleted wafer; and

continuing to pick up said maximum possible feedstocks from said next most depleted wafer until either said product wafer is fully populated with feedstocks of one type or an entire stockpile of a given feedstock has been accessed.

23. The method as recited in claim 1 , wherein said subset of elements from said source wafer has access holes to an underlying sacrificial layer.