Low power active load
View Patent ↗An active load circuit that includes a diode bridge having first through fourth nodes, wherein a voltage buffer is connected with the first node, a source current mirror is connected with the second node, the third node is configured for connection to a device under test (DUT), and a sink current mirror is connected with the fourth node. A first current mirror is connected with the source current mirror, and a second current mirror is connected with the sink current mirror. A first differential pair is connected with the first current mirror and includes an input connected with the DUT and a second input connected with the input voltage. A second differential pair is connected with the second current mirror and includes a first input connected with the DUT and a second input connected with the input voltage.
1. An active load circuit to execute tests on a Device Under Test (DUT), comprising:
a diode bridge having a first node, a second node, a third node, and a fourth node, wherein the first node is opposite to the third node and the second node is opposite to the fourth node, and wherein a voltage buffer, configured to buffer an input voltage, is connected with the first node, a source current mirror is connected with the second node, and a sink current mirror is connected with the fourth node;
a first current mirror connected with the source current mirror and a second current mirror connected with the sink current mirror;
a first differential pair connected with the first current mirror, wherein the first differential pair is fed a first biasing current from a first constant current source, and further wherein the first differential pair has a first input and a second input; and
a second differential pair connected with the second current mirror, wherein the second differential pair is fed a second biasing current from a second constant current source, and further wherein the second differential pair has a third input and a fourth input.
2. The active load circuit of claim 1 , wherein the third node is configured for connection with the DUT.
3. The active load circuit of claim 1 , wherein the first input is configured for connection with the input voltage and the second input is configured for connection with the DUT.
4. The active load circuit of claim 1 , wherein the third input is configured to be connected with the input voltage and the fourth input is configured to be connected with the DUT.
5. The active load circuit of claim 1 , wherein the first constant current source is a constant current circuit.
6. The active load circuit of claim 1 , wherein the second constant current source is a constant current circuit.
7. The active load circuit of claim 1 , wherein a chain of connections between the source current mirror, the first current mirror and the first differential pair follows a configuration selected from a group of series-series connections, series-parallel connections, parallel-series connections and parallel-parallel connections.
8. The active load circuit of claim 1 , wherein a chain of connections between the sink current mirror, the second current mirror and the second differential pair follows a configuration selected from a group of series-series connections, series-parallel connections, parallel-series connections and parallel-parallel connections.
9. The active load circuit of claim 1 , wherein the voltage buffer is a unity gain buffer.
10. The active load circuit of claim 1 , wherein the first current mirror and the first differential pair comprises a pair of transistors each.
11. The active load circuit of claim 10 , wherein the pairs of transistors of the first current mirror and the first differential pair comprise MOSFET type transistors.
12. The active load circuit of claim 11 , wherein the MOSFET type transistors are p-channel MOSFETS.
13. The active load circuit of claim 1 , wherein the second current mirror and the second differential pair comprises a pair of transistors each.
14. The active load circuit of claim 13 , wherein the pairs of transistors of the second current mirror and the second differential pair comprise MOSFET type transistors.
15. The active load circuit of claim 14 , wherein the MOSFET type transistors are n-channel MOSFETS.
16. An active load circuit for performing tests on a Device Under Test (DUT), comprising:
a diode bridge having a first node, a second node, a third node, and a fourth node, wherein the first node is opposite to the third node and the second node is opposite to the fourth node, wherein a voltage buffer configured to buffer an input voltage, is connected with the first node, and a source current mirror is connected with the second node, the third node is configured to connect with the DUT, and a sink current mirror is connected with the fourth node;
a first current mirror connected with the source current mirror and a second current mirror connected with the sink current mirror;
a first differential pair connected with the first current mirror, wherein the first differential pair is fed a first biasing current from a first constant current source, and further wherein the first differential pair has a first input and a second input, wherein the first input is configured to connect with the input voltage and the second input is configured to connect with the DUT; and
a second differential pair connected with the second current mirror, wherein the second differential pair is fed a second biasing current from a second constant current source, and further wherein the second differential pair has a third input and a fourth input, wherein the third input is configured to connect with the input voltage and the fourth input is configured to connect with the DUT.