IP Library › Granted Patent US 10,750,104
Granted Patent B2
US 10,750,104 · App. 16/479,843 · Granted Aug 18, 2020

Solid-state imaging apparatus and driving method thereof

Inventor: Fumiaki Sano (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N5/351H01L27/1461H01L27/14647H01L31/1075
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,750,104
App. No.
16/479,843
Granted
Aug 18, 2020
Kind
B2
Abstract

The present technology relates to a solid-state imaging apparatus and a driving method that can perform imaging at lower power consumption. By providing the solid-state imaging apparatus including a pixel array section on which a plurality of SPAD pixels is two-dimensionally arranged, in which in a case where illuminance becomes first illuminance higher than reference illuminance, a part of the SPAD pixels of the plurality of pixels arranged on the pixel array section is thinned, it is possible to image at lower power consumption. The present technology can be applied to an image sensor, for example.

Claims (31)

1. A solid-state imaging apparatus, comprising:

a pixel array section on which a plurality of SPAD (Single Photon Avalanche Diode) pixels is two-dimensionally arranged, wherein

in a case where illuminance becomes first illuminance higher than reference illuminance, a part of the SPAD pixels of the plurality of pixels arranged on the pixel array section is thinned.

2. The solid-state imaging apparatus according to claim 1 , wherein

in the pixel array section, thinned pixels being the part of the SPAD pixels are thinned for a pixel unit or a block unit including the plurality of pixels.

3. The solid-state imaging apparatus according to claim 2 , wherein

the thinned pixels are arranged regularly or irregularly on the pixel array section for the pixel unit or the block unit.

4. The solid-state imaging apparatus according to claim 2 , wherein

the thinned pixels are thinned by controlling a voltage of an anode or a cathode of each SPAD.

5. The solid-state imaging apparatus according to claim 1 , wherein

the SPAD pixels have a plurality of divided Avalanche sections of the SPADs and are thinned for each divided Avalanche section unit of the divided Avalanche sections.

6. The solid-state imaging apparatus according to claim 5 , wherein

each divided Avalanche section is thinned by controlling a voltage of an anode or a cathode.

7. The solid-state imaging apparatus according to claim 5 , wherein

each divided Avalanche section is thinned by controlling a gate electrode arranged at an upper part of the divided Avalanche section.

8. The solid-state imaging apparatus according to claim 5 , further comprising:

an overflow drain for discharging unnecessary electrons for each divided Avalanche section.

9. The solid-state imaging apparatus according to claim 1 , wherein

a potential difference between the anode and the cathode of the SPAD is controlled for each thinned pixel of the part of the SPAD pixels by using a relationship to an Avalanche probability.

10. The solid-state imaging apparatus according to claim 1 , wherein

the illuminance is classified into a plurality of stages including the first illuminance depending on a reference threshold value.

11. The solid-state imaging apparatus according to claim 10 , wherein

the illuminance is classified into two stages of the first illuminance and a second illuminance lower than the first illuminance depending on the threshold value.

12. The solid-state imaging apparatus according to claim 10 , wherein

the illuminance is classified into three stages of the first illuminance, a second illuminance lower than the first illuminance, and a third illuminance lower than the second illuminance depending on the threshold value.

13. The solid-state imaging apparatus according to claim 1 , wherein

in the SPAD of the SPAD pixels,

an anode is formed at a side of a first surface that is a light incident surface or at a side of a second surface opposite to the first surface, and

a cathode is formed at a side of the second surface or a side of the first side.

14. A driving method of a solid-state imaging apparatus including a pixel array section on which a plurality of SPAD pixels is two-dimensionally arranged, comprising:

in a case where illuminance becomes first illuminance higher than reference illuminance, thinning a part of the SPAD pixels of the plurality of pixels arranged on the pixel array section.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2019
From: SANO, FUMIAKI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 049994/0521 →
Priority Claims (1)
JP 2017-156746 · Aug 15, 2017 · national
Continuity (1)
Related Publication 20200213538A1 · Jul 2, 2020
Cited By (1)
US 12,453,193