Integrating circuit elements in a stacked quantum computing device
A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.
1. A device comprising:
a first chip comprising
a first dielectric substrate and
a qubit on the first dielectric substrate;
a second chip bonded to the first chip, the second chip comprising
a second dielectric substrate,
a qubit readout element on the second dielectric substrate,
a control wire on the second dielectric substrate, wherein a portion of the control wire overlaps the qubit,
a dielectric layer covering the control wire, and
a shielding layer covering the dielectric layer,
wherein the shielding layer is arranged between the portion of the control wire and the qubit to reduce crosstalk between the control wire and the qubit by isolating electromagnetic fields from the control wire and from the qubit from interfering with one another.
2. The device of claim 1 , wherein the dielectric layer comprises an opening through which the qubit readout element is exposed.
3. The device of claim 1 , wherein the dielectric layer comprises a dielectric material having a loss tangent greater than about 10 −5 at a frequency between about 1 GHz and about 10 GHz.
4. The device of claim 1 , wherein the qubit comprises a readout region, and
wherein the qubit readout element overlaps the readout region of the qubit.
5. The device of claim 4 , wherein the qubit readout element comprises a resonator element electrically coupled to a pad element, and wherein the pad element overlaps the readout region of the qubit without the resonator element overlapping the readout region of the qubit.
6. The device of claim 5 , wherein the first chip comprises a ground plane, and wherein the resonator element overlaps the ground plane.
7. The device of claim 1 , wherein the dielectric layer comprises:
a via extending from a surface of the dielectric layer through the dielectric layer to the control wire;
an interconnect within the via and electrically coupled to the control wire; and
a control contact on the surface of the dielectric layer and electrically coupled to the interconnect.
8. The device of claim 7 , wherein the control contact is laterally surrounded by the shielding layer and physically separate from the shielding layer.
9. The device of claim 8 , wherein the control contact overlaps the qubit.
10. The device of claim 9 , wherein the control contact is displaced laterally from the qubit, without overlapping the qubit.
11. The device of claim 1 , wherein the shielding layer covers a sidewall of the dielectric layer.
12. The device of claim 1 , wherein each of the qubit readout element, the control wire, and the shielding layer is a superconductor.
13. The device of claim 1 , wherein the second chip comprises a plurality of control wires and a plurality of dielectric layers,
wherein the plurality of control wires are embedded within the plurality of dielectric layers, and
wherein the shielding layer covers the plurality of dielectric layers.
14. The device of claim 1 , wherein the first chip is bump bonded to the second chip.
15. A quantum computing circuit device comprising:
a first chip comprising
a first dielectric substrate and
a qubit on the first dielectric substrate;
a second chip bonded to the first chip, the second chip comprising:
a second dielectric substrate;
a first superconductor layer on the second dielectric substrate, wherein a first region of the first superconductor layer forms a qubit readout element and a second region of the first superconductor layer forms a qubit control element;
a dielectric layer on the second region of the first superconductor layer;
a via in the dielectric layer to expose a portion of the qubit control element, the via extending from a surface of the dielectric layer to the portion of the qubit control element that is exposed;
a second superconductor layer on the dielectric layer, wherein the second superconductor layer forms an interconnect within the via, the interconnect contacting the portion of the qubit control element that is exposed, and wherein the second superconductor layer forms a shielding layer that is electrically isolated from the interconnect
wherein the shielding layer is arranged between the portion of the qubit control element and the qubit on the first chip to reduce crosstalk between the portion of the qubit control element and the qubit by isolating electromagnetic fields from the qubit control element and from the qubit from interfering with one another.