Chip-carrier socket for microfluidic-cooled three-dimensional electronic/photonic integrated circuits

1. A chip carrier socket for an electronic-photonic integrated-circuit assembly, the chip carrier socket comprising:

a carrier bottom comprising one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each of the conductive vias being configured to provide electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom; and

a carrier top configured to mate to the carrier bottom while enclosing the electronic-photonic integrated-circuit assembly within an enclosed cavity formed by the mating of the carrier top and carrier bottom;

wherein one or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port, the fluid inlet port and fluid outlet port each being configured to allow passage of cooling fluid between the interior and exterior of the enclosed cavity formed by the mating of the carrier top and carrier bottom, and

wherein one or both of the carrier bottom and the carrier top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.

2. The chip carrier socket of claim 1 , wherein a conductive contact on the carrier top is configured to engage a corresponding conductive contact on the carrier bottom when the carrier top is mated to the carrier bottom, and wherein the corresponding conductive contact on the carrier bottom is conductively connected to a pad, solder ball, electrically conductive spring, or conductive lead, on or adjacent to the second surface of the carrier bottom.

3. The chip carrier socket of claim 2 , wherein the conductive contact on the carrier top comprises a spring-loaded, electrically conductive plug.

4. The chip carrier socket of claim 1 , wherein the carrier top comprises a fluid inlet port and a fluid outlet port, the fluid inlet port and fluid outlet port of the carrier top being configured to allow passage of cooling fluid between the interior and exterior of the enclosed cavity formed by the mating of the carrier top and carrier bottom.

5. The chip carrier socket of claim 4 , wherein the fluid inlet port and fluid outlet port of the carrier top are arranged to align with corresponding fluid inlet and outlet ports on the electronic-photonic integrated-circuit assembly, when the electronic-photonic integrated-circuit assembly is enclosed within the enclosed cavity formed by the mating of the carrier top and bottom.

6. The chip carrier socket of claim 1 , wherein the carrier bottom comprises a fluid inlet port and a fluid outlet port configured to allow passage of cooling fluid between the interior and exterior of the enclosed cavity formed by the mating of the carrier top and carrier bottom.

7. The chip carrier socket of claim 6 , wherein the fluid inlet port and fluid outlet port of the carrier bottom are arranged to align with corresponding fluid inlet and outlet ports on the electronic-photonic integrated-circuit assembly, when the electronic-photonic integrated-circuit assembly is enclosed within the enclosed cavity formed by the mating of the carrier top and bottom.

8. The chip carrier socket of claim 1 , further comprising a microfluidic pump coupled to the carrier top or carrier bottom and in fluid connection with a fluid inlet port or fluid outlet port.

9. The chip carrier socket of claim 8 , wherein the microfluidic pump is replaceably removable from the carrier top or carrier bottom.

10. The chip carrier socket of claim 1 , wherein the carrier top comprises an optical via passing from a first surface of the carrier top to a second surface of the carrier top and arranged to couple to an optical port on the electronic-photonic integrated-circuit assembly, when the electronic-photonic integrated-circuit assembly is enclosed within the enclosed cavity formed by the mating of the carrier top and bottom.

11. The chip carrier socket of claim 1 , wherein the carrier bottom comprises an optical via passing from one surface of the carrier bottom to another surface of the carrier bottom.

12. The chip carrier socket of claim 11 , wherein the optical via passing from one surface of the carrier bottom to another surface of the carrier bottom passes from the first surface of the carrier bottom to the second surface of the carrier bottom.

13. The chip carrier socket of claim 12 , wherein the optical via passing from one surface of the carrier bottom to another surface of the carrier bottom passes from the first surface of the carrier bottom to a third surface of the carrier bottom, the third surface being generally orthogonal to the first and second surfaces.

14. The chip carrier socket of claim 12 , wherein the optical via passing from one surface of the carrier bottom to another surface of the carrier bottom passes from a third surface of the carrier bottom to a fourth surface of the carrier bottom, wherein the third and fourth surfaces are generally orthogonal to both the first and second surfaces and opposite one another with respect to the enclosed cavity formed by the mating of the carrier top and bottom.

15. An assembly comprising the chip carrier socket of claim 1 and further comprising the electronic-photonic integrated-circuit assembly, the electronic-photonic integrated-circuit assembly being disposed within the enclosed cavity formed by the mating of the carrier top and carrier bottom.

16. The assembly of claim 15 , wherein the electronic-photonic integrated-circuit assembly comprises:

two or more integrated-circuit dies bonded to one another so as to form a die stack with first and second primary exterior surfaces corresponding, respectively, to an outer surface of a first one of the integrated-circuit dies and to an outer surface of a second one of the integrated-circuit dies, at least one of the two or more integrated-circuit dies comprising one or more integrated photonic devices; and

a carrier substrate;

wherein one or more channels or passages are formed into the outer surface of the first one of the integrated-circuit dies, and wherein a first surface of the carrier substrate is bonded to the outer surface of the first one of the integrated-circuit dies, thereby enclosing the one or more channels or passages; and

wherein each of the two or more integrated-circuit dies is electrically connected to at least one other integrated-circuit die via an electrically conductive through-wafer interconnect or an electrically conductive through-wafer via.

17. A printed circuit board assembly for providing an integrated chip carrier socket for an electronic-photonic integrated-circuit assembly, the printed circuit board assembly comprising:

a carrier bottom integrated into a printed circuit board and comprising one or more conductive vias passing from a first surface of the carrier bottom to corresponding electrical traces in or on the printed circuit board; and

a carrier top configured to mate to the carrier bottom while enclosing the electronic-photonic integrated-circuit assembly within an enclosed cavity formed by the mating of the carrier top and carrier bottom;

wherein one or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port, the fluid inlet port and fluid outlet port each being configured to allow passage of cooling fluid between the interior and exterior of the enclosed cavity formed by the mating of the carrier top and carrier bottom, and

wherein one or both of the carrier bottom and the carrier top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.