Semiconductor package with guide pin
A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.
1. A semiconductor package, comprising:
one or more substrates coupled together;
one or more pressfit pins coupled to the one or more substrates; and
two or more guide pins coupled directly on a first side of the one or more substrates;
wherein the two or more guide pins have a height greater than the one or more pressfit pins.
2. The semiconductor package of claim 1 , wherein the two or more guide pins are coupled around a perimeter of a first side of the one or more substrates.
3. The semiconductor package of claim 1 , further comprising:
a first guide pin of the two or more guide pins coupled near a corner of a first substrate of the one or more substrates;
a second guide pin of the two or more guide pins coupled on a side of a second substrate of the one or more substrates; and
a third guide pin of the two or more guide pins coupled near a corner of a third substrate of the one or more substrates;
wherein the first guide pin, second guide pin, and third guide pin are aligned on a line passing diagonally across the first substrate, second substrate, and third substrate.
4. The semiconductor package of claim 1 , wherein the one or more pressfit pins and the two or more guide pins extend through a cover coupled over the one or more substrates.
5. The semiconductor package of claim 1 , further comprising:
a first guide pin of the two or more guide pins coupled near a corner of a first substrate of the one or more substrates;
a second guide pin of the two or more guide pins coupled near a first corner of a second substrate of the one or more substrates;
a third guide pin of the two or more guide pins coupled near a second corner of the second substrate;
a fourth guide pin of the two or more guide pins coupled near a corner of a third substrate of the one or more substrates;
wherein the first guide pin and the second guide pin, along with the third guide pin and the fourth guide pin are aligned in a paired diagonal configuration.
6. The semiconductor package of claim 1 , further comprising a plurality of die coupled to the one or more substrates.
7. The semiconductor package of claim 1 , wherein each of the two or more guide pins comprises a stress relief portion coupled to the one or more substrates.
8. A semiconductor package, comprising:
one or more substrates coupled together;
one or more pressfit pins coupled to the one or more substrates; and
two or more guide pins directly coupled to the one or more substrates;
wherein the two or more guide pins are configured to align the one or more pressfit pins with corresponding openings in a printed circuit board.
9. The semiconductor package of claim 8 , wherein the two or more guide pins are coupled on a first side of the one or more substrates and extend therefrom.
10. The semiconductor package of claim 8 , further comprising:
a first guide pin of the two or more guide pins coupled near a corner of a first substrate of the one or more substrates;
a second guide pin of the two or more guide pins coupled on a side of a second substrate of the one or more substrates; and
a third guide pin of the two or more guide pins coupled near a corner of a third substrate of the one or more substrates;
wherein the first guide pin, second guide pin, and third guide pin are aligned on a line passing diagonally across the first substrate, second substrate, and third substrate.
11. The semiconductor package of claim 8 , wherein the one or more pressfit pins and the two or more guide pins extend through a cover coupled over the one or more substrates.
12. The semiconductor package of claim 8 , further comprising:
a first guide pin of the two or more guide pins coupled near a corner of a first substrate of the one or more substrates;
a second guide pin of the two or more guide pins coupled near a first corner of a second substrate of the one or more substrates;
a third guide pin of the two or more guide pins coupled near a second corner of the second substrate;
a fourth guide pin of the two or more guide pins coupled near a corner of a third substrate of the one or more substrates;
wherein the first guide pin and the second guide pin, along with the third guide pin and the fourth guide pin are aligned in a paired diagonal configuration.
13. The semiconductor package of claim 8 , further comprising a plurality of die coupled to the one or more substrates.
14. The semiconductor package of claim 8 , wherein each of the two or more guide pins comprises a stress relief portion coupled to the one or more substrates.
15. A semiconductor guide pin, comprising:
a first portion coupled with a stress relief portion, the stress relief portion configured to be coupled to a substrate or a heatsink;
wherein the first portion is configured to extend into an opening in a printed circuit board to align a plurality of pressfit pins with a plurality of openings in the printed circuit board; and
wherein the guide pin is configured to be electrically isolated when coupled to the substrate.
16. The guide pin of claim 15 , wherein the stress relief portion comprises a waved shape.
17. The guide pin of claim 15 , wherein the stress relief portion comprises a stop.
18. The guide pin of claim 15 , wherein a first end of the first portion is beveled.