IP Library Granted Patent US 11,101,197
Granted Patent B2
US 11,101,197 · App. 16/504,929 · Granted Aug 24, 2021

Leadframe systems and related methods

Inventors: Hiroshi Inoguchi (Tatebayashi, JP); Isao Ochiai (Ota, JP); Takayuki Taguchi (Hanyu, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49513H01L21/4821H01L21/565H01L23/3107H01L23/49568
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Quick Facts
Patent No.
US 11,101,197
App. No.
16/504,929
Granted
Aug 24, 2021
Kind
B2
Abstract

Leadframe systems and related methods. Specific implementations of leadframe systems may include a die pad, a semiconductor die coupled to the die pad, where the semiconductor die has a perimeter. A leadframe may be coupled over the die pad and the semiconductor die where the leadframe has a solder dam coupled around the semiconductor die and, the solder dam has a perimeter that corresponds with the semiconductor die The die pad may have no groove adjacent to the semiconductor die.

Claims (31)

1. A semiconductor package comprising:

a die pad;

a semiconductor die coupled to the die pad, the semiconductor die having a perimeter; and

a leadframe coupled over the die pad and the semiconductor die, the leadframe comprising a solder dam coupled around the semiconductor die, the solder dam comprising an opening having a perimeter greater than the perimeter of the semiconductor die.

2. The semiconductor package of claim 1 , further comprising solder, wherein the solder is configured to be deposited within the solder dam without a spanker.

3. The semiconductor package of claim 2 , wherein the solder is flux-contained.

4. The semiconductor package of claim 1 , wherein the die pad is plated with a metal.

5. The semiconductor package of claim 1 , wherein the die pad, the semiconductor die, and the leadframe are encapsulated in an encapsulant.

6. A method of making a semiconductor package comprising:

providing a die pad;

coupling a leadframe over the die pad, the die pad separate from the leadframe and the leadframe comprising a solder dam having a first perimeter;

depositing solder into the solder dam;

bonding a semiconductor die to the solder within the first perimeter; and

retaining the solder under the semiconductor die using the solder dam.

7. The method of claim 6 , wherein the die pad comprises no groove adjacent to the semiconductor die.

8. The method of claim 6 , further comprising preventing tilt of the semiconductor die through retaining the solder using the solder dam.

9. The method of claim 6 , wherein the first perimeter is greater than a second perimeter of the semiconductor die.

10. The method of claim 6 , wherein the solder dam comprises an opening within the leadframe, the opening having the first perimeter greater than a second perimeter of the semiconductor die.

11. The method of claim 6 , further comprising encapsulating the die pad, the semiconductor die, and the leadframe in an encapsulant.

12. The method of claim 6 , further comprising plating the die pad with a metal.

13. The method of claim 6 , wherein coupling the leadframe over the die pad further comprises passing the die pad through an opening in the leadframe, the opening comprising a solder dam opening.

14. A method of providing a heatsink for a semiconductor package, the method comprising:

providing a leadframe having a solder dam opening therethrough, the leadframe having a first thickness; and

bonding a first heatsink with the leadframe, the first heatsink having a second thickness that is the same as the first thickness;

wherein a volume of the leadframe and the first heatsink is the same as a volume of a leadframe without a solder dam opening therethrough and a second heatsink.

15. The method of claim 14 , wherein the solder dam opening has a perimeter a predetermined distance greater than a perimeter of a semiconductor die, wherein the solder dam opening prevents a flow of solder.

16. The method of claim 14 , wherein no spanker is used after depositing solder into the solder dam opening.

17. The method of claim 14 , wherein a combined thickness of the leadframe and the first heatsink is two-thirds of a combined thickness of the leadframe without the solder dam opening and the first heatsink.

18. The method of claim 14 , further comprising bonding a semiconductor die to solder within a perimeter of the solder dam opening.

19. The method of claim 18 , further comprising encapsulating at least the leadframe in an encapsulant.

20. The method of claim 18 , further comprising preventing tilt of a semiconductor die through retaining the solder with the solder dam opening.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 051145, FRAME 0062 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064079/0474 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXCLUSION OF FAIRCHILD SEMICONDUCTOR CORPORATION OF CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 051145 FRAME 0062. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Dec 3, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051170/0781 →
SECURITY INTEREST Recorded Nov 26, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051145/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2019
From: INOGUCHI, HIROSHI; OCHIAI, ISAO; TAGUCHI, TAKAYUKI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 049690/0016 →