Processing device, network node, client device, and methods thereof
This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.
1. A network node, comprising:
a transceiver; and
a processing device coupled to the transceiver, the processing device being configured to generate a primary synchronization signal (PSS) sequence for a PSS and a secondary synchronization signal (SSS) sequence for an SSS,
wherein the SSS sequence is associated with a first cyclic shift m 0 and a second cyclic shift m 1 , and wherein m 0 and m 1 satisfy:
m
0
=
g
(
N
ID
,
max
(
2
)
⌊
N
ID
(
1
)
L
′
⌋
+
N
ID
(
2
)
)
;
m
1
=
(
N
ID
(
1
)
mod
L
′
)
wherein:
g is an integer equal to or larger than 1;
L′ is 112;
N ID (1) ∈{0, 1, 2, . . . , N ID,max (1) −1}; and
N ID (2) ∈{0, 1, . . . , N ID,max (2) −1}; and
the transceiver being configured to transmit the PSS based on the PSS sequence and the SSS based on the SSS sequence.
2. The network node according to claim 1 , wherein the PSS sequence is associated with N ID (2) .
3. The network node according to claim 1 , wherein the first cyclic shift m 0 and the second cyclic shift m 1 are associated with a cell ID N ID , wherein N ID =3 N ID (1) +N ID (2) .
4. The network node according to claim 1 , wherein the processing device is configured to generate the SSS sequence for the SSS based on a first sequence cyclically shifted by the first cyclic shift m 0 and a second sequence cyclically shifted by the second cyclic shift m 1 , the first sequence and the second sequence having the same length.
5. The network node according to claim 4 , wherein the first and the second sequences are m-sequences.
6. The network node according to claim 4 , wherein a generator polynomial of the first sequence is g 0 (x)=x 7 +x 4 +1, and a generator polynomial of the second sequence is g 1 (x)=x 7 +x+1.
7. The network node according to claim 4 , wherein a generator polynomials of the PSS sequence is same with one of the generator polynomials of the first and the second sequences.
8. The network node according to claim 1 , wherein the PSS sequence is one of three PSS sequences.
9. The network node according to claim 1 , wherein the Length L of the SSS sequence is 127.
10. The network node according to claim 1 , wherein N ID,max (2) is 3, and N ID (2) ∈{0, 1, 2}.
11. The network node according to claim 1 , wherein N ID,max (1) is 336, and N ID (1) ∈{0, 1, 2, . . . , 335}.
12. A processing device for wireless communications, comprising:
at least one processor configured to:
determine a first cyclic shift m 0 and a second cyclic shift m 1 ; and
generate a secondary synchronization signal (SSS) sequence for an SSS,
wherein the SSS sequence is associated with the first cyclic shift m 0 and the second cyclic shift m 1 , and wherein m 0 and m 1 satisfy:
m
0
=
g
(
N
ID
,
max
(
2
)
⌊
N
ID
(
1
)
L
′
⌋
+
N
ID
(
2
)
)
;
m
1
=
(
N
ID
(
1
)
mod
L
′
)
wherein:
g is an integer equal to or larger than 1;
L′ is 112;
N ID (1) ∈{0, 1, 2, . . . , N ID,max (1) −1}; and
N ID (2) ∈{0, 1, . . . , N ID,max (2) −1}.
13. The processing device according to claim 12 , wherein the at least one processor comprises at least one of the following defining operational logic:
an application specific integrated circuitry (ASIC);
a central processing unit (CPU) coupled to retrieve instructions from a memory, and processing logic that may interpret and execute instructions.
14. The processing device according to claim 12 , wherein the at least one processor is configured to generate a primary synchronization signal (PSS) sequence for a PSS, the PSS sequence being associated with N ID (2) .
15. The processing device according to claim 12 , wherein the first cyclic shift m 0 and the second cyclic shift m 1 are associated with a cell ID N ID , wherein N ID =3 N ID (1) +N ID (2) .
16. The processing device according to claim 12 , wherein the at least one processor is configured to generate the SSS sequence for the SSS based on a first sequence cyclically shifted by the first cyclic shift m 0 and a second sequence cyclically shifted by the second cyclic shift m 1 , the first sequence and the second sequence having the same length.
17. The processing device according to claim 16 , wherein the first and the second sequences are m-sequences.
18. The processing device according to claim 16 , wherein a generator polynomial of the first sequence is g 0 (x)=x 7 +x 4 +1, and a generator polynomial of the second sequence is g 1 (x)=x 7 +x+1.
19. The processing device according to claim 16 , wherein a generator polynomials of the PSS sequence is same with one of the generator polynomials of the first and the second sequences.
20. The processing device according to claim 12 , wherein the Length L of the SSS sequence is 127.
21. The processing device according to claim 12 , wherein N ID,max (2) is 3, and N ID (2) ∈{0, 1, 2}.
22. The processing device according to claim 12 , wherein N ID,max (1) is 336, and N ID (1) ∈{0, 1, 2, . . . , 335}.
23. A non-transitory computer readable medium, comprising computer instructions that, when executed by a processor, cause the processor to
determine a first cyclic shift m 0 and a second cyclic shift m 1 ; and
generate a secondary synchronization signal (SSS) sequence for an SSS,
wherein the SSS sequence is associated with the first cyclic shift m 0 and the second cyclic shift m 1 , and wherein m 0 and m 1 satisfy:
m
0
=
g
(
N
ID
,
max
(
2
)
⌊
N
ID
(
1
)
L
′
⌋
+
N
ID
(
2
)
)
;
m
1
=
(
N
ID
(
1
)
mod
L
′
)
wherein:
g is an integer equal to or larger than 1;
L′ is 112;
N ID (1) ∈{0, 1, 2, . . . , N ID,max (1) −1}; and
N ID (2) ∈{0, 1, . . . , N ID,max (2) −1}.
24. The non-transitory computer readable medium according to claim 23 , further comprising computer instructions for causing the processor to generate the SSS sequence formed with a first sequence corresponding to the first cyclic shift m 0 and a second sequence corresponding to the second cyclic shift m 1 .
25. The non-transitory computer readable medium according to claim 24 , wherein a generator polynomial of the first sequence is g 0 (x)=x 7 +x 4 +1, and a generator polynomial of the second sequence is g 1 (x)=x 7 +x+1.
26. The non-transitory computer readable medium according to claim 24 , further comprising computer instructions for causing the processor to generate a primary synchronization signal (PSS) sequence, wherein a generator polynomials of the PSS sequence is same with one of the generator polynomials of the first and the second sequences.
27. The non-transitory computer readable medium according to claim 24 , wherein the first cyclic shift m 0 and the second cyclic shift m 1 are associated with a cell ID N ID , wherein N ID =3 N ID (1) +N ID (2) .
28. The non-transitory computer readable medium according to claim 25 , wherein N ID,max (2) is 3, and N ID (2) ∈{0, 1, 2}.
29. The non-transitory computer readable medium according to claim 25 , wherein N ID,max (1) is 336, and N ID (1) ∈{0, 1, 2, . . . , 335}.
30. The non-transitory computer readable medium according to claim 25 , wherein an SSS sequence for the SSS has a length L of 127.