IP Library Granted Patent US 10,755,956
Granted Patent B2
US 10,755,956 · App. 16/505,967 · Granted Aug 25, 2020

Backside wafer alignment methods

Inventors: Michael J. Seddon (Gilbert, AZ); Takashi Noma (Ota, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/681H01L21/76871H01L21/78
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Quick Facts
Patent No.
US 10,755,956
App. No.
16/505,967
Granted
Aug 25, 2020
Kind
B2
Abstract

Implementations of a method for wafer alignment may include: providing a wafer having a first side and a second side and forming a seed layer on a second side of the wafer. The method may include applying a glop to the seed layer at two or more predetermined points and plating a metal layer over the seed layer and around the glop. The method may include removing the glop to expose the seed layer and etching the seed layer to expose a plurality of alignment features on the second side of the wafer.

Claims (39)

1. A method for wafer alignment, the method comprising:

providing a wafer comprising a first side and a second side;

forming a seed layer on a second side of the wafer;

applying a glop to the seed layer at two or more predetermined points;

plating a metal layer over the seed layer and around the glop;

removing the glop to expose the seed layer;

etching the seed layer to expose a plurality of alignment features in the wafer.

2. The method of claim 1 , further comprising using the plurality of alignment features to align the wafer for singulation.

3. The method of claim 1 , wherein applying the glop further comprises using one of a stencil, a motor controlled dispenser, or a spray coater.

4. The method of claim 1 , wherein the metal layer comprises one of gold, copper, nickel, or any combination thereof.

5. The method of claim 1 , wherein the glop comprises, photoresist, resin, or polymeric material.

6. A method for wafer alignment, the method comprising:

providing a wafer comprising one or more die streets on a first side of the wafer and a seed metal layer on a second side of the wafer;

applying a glop to an area of the second side of the wafer corresponding with the one or more die streets on the first side of the wafer;

forming a layer of metal on the seed metal layer; and

etching the seed metal layer to expose two of the one or more die streets, the two of the one or more die streets each comprising a plurality of alignment features therein.

7. The method of claim 6 , further comprising:

aligning the wafer using an infrared camera; and

singulating the wafer into a plurality of die.

8. The method of claim 6 , wherein applying the glop further comprises using one of a stencil, a motor controlled dispenser, or a spray coater.

9. The method of claim 6 , wherein the metal layer comprises one of gold, copper, nickel, or any combination thereof.

10. The method of claim 6 , wherein the glop comprises, photoresist, resin, or polymeric material.

11. A method for wafer alignment, the method comprising:

providing a wafer comprising a first side and a second side;

applying a wafer backside coating to a second side of the wafer;

applying a glop to the wafer backside coating at two or more predetermined points;

plating a metal layer over the wafer backside coating and around the glop;

removing the glop to expose the wafer backside coating; and

removing the wafer backside coating to expose a plurality of alignment features in the wafer.

12. The method of claim 11 , further comprising:

aligning the wafer using an infrared camera; and

singulating the wafer into a plurality of die.

13. The method of claim 11 , wherein applying the glop further comprises using one of a stencil, a motor controlled dispenser, or a spray coater.

14. The method of claim 11 , wherein the metal layer comprises one of gold, copper, nickel, or any combination thereof.

15. The method of claim 11 , wherein the glop comprises, photoresist, resin, or polymeric material.

16. The method of claim 11 , wherein the wafer backside coating is a seed metal layer.

17. The method of claim 16 , wherein removing the seed metal layer comprises etching.

18. The method of claim 11 , wherein the wafer backside coating is opaque.

19. The method of claim 11 , wherein the metal layer comprises one of metal, oxides, or polymeric materials.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 051145, FRAME 0062 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064079/0474 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXCLUSION OF FAIRCHILD SEMICONDUCTOR CORPORATION OF CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 051145 FRAME 0062. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Dec 3, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051170/0781 →
SECURITY INTEREST Recorded Nov 26, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 051145/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2019
From: SEDDON, MICHAEL J.; NOMA, TAKASHI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 049698/0762 →