Semiconductor memory device having an array chip bonded to a circuit chip by a bonding metal
View Patent ↗According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
1. A semiconductor memory device comprising:
an array chip including
a three-dimensionally disposed plurality of memory cells,
a memory-side interconnection layer provided below the memory cells and connected to the memory cells,
a stacked body including a plurality of electrode layers stacked via an insulating layer,
a semiconductor body extending in a stacking direction of the stacked body in the stacked body,
a charge storage film provided between the semiconductor body and the electrode layers,
a bit line connected to an end portion of the semiconductor body, and
a source line connected to another end portion of the semiconductor body;
a circuit chip including a substrate, a MOS transistor provided on the substrate, and a circuit-side interconnection layer provided above the MOS transistor and connected to the MOS transistor, the circuit chip provided below the array chip and stuck to the array chip, the circuit-side interconnection layer provided below the memory-side interconnection layer of the array chip;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad included in the memory-side interconnection layer of the array chip; and
an external connection electrode provided on the array chip, the external connection electrode electrically connected to the pad, wherein
the electrode layers are formed in a step shape at an end of a memory cell array region where the memory cells are disposed,
the memory-side interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape,
the bonding metal includes a bit-line lead-out section electrically connected to the bit line, and
the bit-line lead-out section is disposed in a region overlapping the memory cell array region in the stacking direction.
2. The device according to claim 1 , wherein the pad is provided in a same layer as the word interconnection layers and formed of a same material as the word interconnection layers.
3. The device according to claim 1 , wherein
a gate layer is provided in a layer on an opposite side of the memory-side interconnection layer in the stacked body.
4. The device according to claim 1 , further comprising an insulating film provided around the bonding metal.
5. A semiconductor memory device comprising:
an array chip including
a three-dimensionally disposed plurality of memory cells,
a memory-side interconnection layer provided below the memory cells and connected to the memory cells,
a stacked body including a plurality of electrode layers stacked via an insulating layer,
a semiconductor body extending in a stacking direction of the stacked body in the stacked body,
a charge storage film provided between the semiconductor body and the electrode layers,
a bit line connected to an end portion of the semiconductor body, and
a source line connected to another end portion of the semiconductor body;
a circuit chip including a substrate, a MOS transistor provided on the substrate, and a circuit-side interconnection layer provided above the MOS transistor and connected to the MOS transistor, the circuit chip provided below the array chip and stuck to the array chip, the circuit-side interconnection layer provided below the memory-side interconnection layer of the array chip;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad included in the memory-side interconnection layer of the array chip; and
an external connection electrode provided on the array chip, the external connection electrode electrically connected to the pad, wherein
the electrode layers are formed in a step shape at an end of a memory cell array region where the memory cells are disposed,
the memory-side interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape,
the bonding metal includes a plurality of word-line lead-out sections electrically connected to the word interconnection layers, and
the pad is provided in a region overlapping the word-line lead-out sections in the stacking direction.
6. The device according to claim 5 , wherein the pad is provided in a same layer as the word interconnection layers and formed of a same material as the word interconnection layers.
7. The device according to claim 5 , wherein
a gate layer is provided in a layer on an opposite side of the memory-side interconnection layer in the stacked body.
8. The device according to claim 5 , further comprising an insulating film provided around the bonding metal.
9. A semiconductor memory device comprising:
an array chip including
a three-dimensionally disposed plurality of memory cells,
a memory-side interconnection layer provided below the memory cells and connected to the memory cells,
a stacked body including a plurality of electrode layers stacked via an insulating layer,
a semiconductor body extending in a stacking direction of the stacked body in the stacked body,
a charge storage film provided between the semiconductor body and the electrode layers,
a bit line connected to an end portion of the semiconductor body, and
a source line connected to another end portion of the semiconductor body;
a circuit chip including a substrate, a MOS transistor provided on the substrate, and a circuit-side interconnection layer provided above the MOS transistor and connected to the MOS transistor, the circuit chip provided below the array chip and stuck to the array chip, the circuit-side interconnection layer provided below the memory-side interconnection layer of the array chip;
a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;
a pad included in the memory-side interconnection layer of the array chip, wherein
the pad is provided in a same layer as the source line and formed of a same material as the source line; and
an external connection electrode provided on the array chip, the external connection electrode electrically connected to the pad.
10. The device according to claim 9 , wherein
a gate layer is provided in a layer on an opposite side of the memory-side interconnection layer in the stacked body.
11. The device according to claim 9 , further comprising an insulating film provided around the bonding metal.