Electronic Device Including a Conductive Layer Including a Ta Si Compound and a Process of Forming the Same
An electronic device can include a first layer including a III-V material, and a conductive layer including a first film that contacts the first layer, wherein the first film includes Ta—Si compound. In an embodiment, the electronic device can be a high electron mobility transistor (HEMT), the first layer can be a barrier layer between a channel layer and the source and drain electrodes. The source and drain electrodes are formed from the conductive layer. In a particular embodiment, the barrier layer can include AlGaN and be undoped or unintentional doped, and a Ta—Si compound can be the first film that contacts AlGaN within the barrier layer. The Ta—Si compound allows for relatively low contact resistance to be achieved without a relatively high temperature anneal or unusual sensitivity to the thickness of the first film that contains the Ta—Si compound.
1 . An electronic device comprising:
a first layer including Al z Ga (1-z) N, wherein 0.02≤z≤0.5, wherein the first layer is undoped or has a dopant concentration at most 1×10 16 atoms/cm 3 ; and
a conductive layer including a first film that contacts the first layer at a plurality of locations, wherein the first film includes a Ta—Si compound, and the first and conductive layers have a corresponding median contact resistance of at most 0.40 ohm·mm.
2 . The electronic device of claim 1 , wherein the first and conductive layers has a corresponding median contact resistance of at most 0.35 ohm·mm.
3 . The electronic device of claim 1 , wherein the first and conductive layers has a corresponding median contact resistance of at most 0.30 ohm·mm.
4 . The electronic device of claim 1 , wherein the first and conductive layers has a corresponding median contact resistance is at least 0.20 ohm·mm.
5 . The electronic device of claim 1 , wherein the Ta—Si compound has a formula of TaSi x , wherein x is in a range of 1.5 to 3.0.
6 . The electronic device of claim 1 , wherein the first film has a thickness of at least 6 nm.
7 . The electronic device of claim 6 , wherein the first film has a thickness of at most 40 nm.
8 . The electronic device of claim 1 , wherein the conductive layer further comprises a second film that includes at least 90 wt % Al.
9 . The electronic device of claim 8 , wherein the conductive layer further comprises a third film, wherein the second film is disposed between the first and third films, and the third film has a composition different from each of the second film.
10 . The electronic device of claim 1 , wherein the first layer includes Al z Ga (1-z) N, where 0.11≤z≤0.3.
11 . The electronic device of claim 1 , comprising a high electron mobility transistor that includes the first layer.
12 . The electronic device of claim 11 , wherein the high electron mobility transistor comprises a channel layer that includes a III-V compound, wherein the first layer is disposed between the channel layer and the conductive layer.
13 . The electronic device of claim 12 , wherein the channel layer is a GaN layer.
14 . The electronic device of claim 12 , a source electrode of the high electron mobility transistor, a drain electrode of the high electron mobility transistor, or both the source and drain electrodes include the conductive layer.
15 . The electronic device of claim 14 , wherein the high electron mobility transistor further comprises a gate electrode having a different composition as compared to the source and drain electrodes.
16 . An electronic device comprising:
a high-electron mobility transistor including:
a channel layer including GaN;
a barrier layer overlying the channel layer and including Al x Ga (1-x) N, where 0.11≤x≤0.3;
a source electrode contacting the barrier layer; and
a drain electrode spaced apart from the source electrode and contacting the barrier layer,
wherein the source electrode, the drain electrode, or both the source and drain electrodes include a conductive layer that includes a first film contacting the barrier layer and including a Ta—Si compound, and a second film that includes at least 90 wt % Al, and a median contact resistance for the barrier layer and either or both of the source and drain electrodes is at most 0.40 ohm·mm.
17 . The electronic device of claim 16 , wherein a median contact resistance for the barrier layer and either or both of the source and drain electrodes is at most 0.30 ohm·mm.
18 . A process of forming an electronic device comprising:
providing a first layer over a substrate, wherein the first layer includes Al z Ga (1-z) N, wherein 0.02≤z≤0.5 and is undoped or has a dopant concentration at most 1×10 16 atoms/cm 3 ; and
forming a conductive layer including a first film that contacts the first layer at a plurality of locations, wherein the first film includes a Ta—Si compound, and the first and conductive layers have a corresponding median contact resistance of at most 0.40 ohm·mm.
19 . The process of claim 18 , wherein forming the conductive layer further comprises:
forming the first film, wherein the Ta—Si compound has a formula of TaSi x , wherein x is in a range of 1.0 to 3.0;
forming a second film over the first film, wherein the second film includes at least 90 wt % Al; and
forming a third film over the second film.
20 . The process of claim 18 , further comprising annealing the first and conductive layers at a temperature in a range of 620° C. to 890° C. for a time in a range of 60 s to 300 s, wherein the median contact resistance for the first and conductive layers is at most 0.30 ohm·mm.