Semiconductor device and method of manufacturing the same
A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
1. A semiconductor device, comprising:
semiconductor wires disposed over a channel region on a substrate;
a source/drain epitaxial layer in contact with the semiconductor wires which do not pass through the source/drain epitaxial layer;
a gate structure in the channel region, the gate structure comprising:
a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region; and
a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and
dielectric spacers including one or more of silicon nitride and silicon oxide, SiON, SiOC, SiCN or SiOCN and disposed in recesses formed between the source/drain epitaxial layer and the gate structure at both ends of the channel region,
wherein an end of each of the dielectric spacers facing the source/drain epitaxial layer is convex toward the source/drain epitaxial layer.
2. The semiconductor device of claim 1 , wherein the recesses are formed in a region between the gate electrode layer and the source/drain epitaxial layer.
3. The semiconductor device of claim 1 , wherein the source/drain epitaxial layer comprises one or more of Si, SiGe and SiGeB.
4. The semiconductor device of claim 1 , wherein the gate electrode layer comprises one of poly silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof.
5. The semiconductor device of claim 1 , wherein another end of each of the dielectric spacers facing the gate dielectric layer is concave toward the gate dielectric layer.
6. The semiconductor device of claim 1 , wherein the dielectric spacers are in direct contact with the source/drain epitaxial layer.
7. The semiconductor device of claim 1 , wherein a semiconductor layer made of a different material from the semiconductor wires is disposed between the source/drain epitaxial layer and the end of each of the dielectric spacers.
8. A semiconductor device, comprising:
semiconductor wires disposed over a channel region on a substrate;
a source/drain epitaxial layer in contact with the semiconductor wires which pass through the source/drain epitaxial layer, wherein the source/drain epitaxial layer wraps around the semiconductor wires;
a gate structure in the channel region, the gate structure comprising:
a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region; and
a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and
inner spacers disposed in recesses formed between the source/drain epitaxial layer and the gate structure at both ends of the channel region.
9. The semiconductor device of claim 8 , wherein the inner spacers comprise a dielectric layer.
10. The semiconductor device of claim 9 , wherein the dielectric layer of the inner spacers comprises at least one of silicon nitride and silicon oxide.
11. The semiconductor device of claim 8 , wherein the inner spacers have a convex outer surface toward the source/drain epitaxial layer.
12. The semiconductor device of claim 8 , wherein the inner spacers comprise at least one of SiOC, SiOCN and SiCN.
13. The semiconductor device of claim 8 , wherein the inner spacers have one of a concave or flat outer surface toward the gate dielectric layer.
14. The semiconductor device of claim 8 , wherein the semiconductor wires have a thickness in a range from about 5 nm to about 15 nm and a width in a range from about 5 nm to about 15 nm.
15. The semiconductor device of claim 8 , wherein the inner spacers in contact with the source/drain epitaxial layer have a facet including <100>, <110>, and <001>.
16. The semiconductor device of claim 8 , wherein the semiconductor wires are made of Si or SiGe.
17. A semiconductor device, comprising:
semiconductor wires disposed over a channel region on a substrate;
a source/drain epitaxial layer in contact with the semiconductor wires and wrapping around the semiconductor wires;
a gate structure in the channel region, the gate structure comprising:
a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region; and
a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and
dielectric spacers including one or more of silicon nitride and silicon oxide, SiON, SiOC, SiCN or SiOCN and disposed in recesses formed between the source/drain epitaxial layer and the gate structure, wherein:
the dielectric spacers are disposed inside the source/drain epitaxial layer, and
an end of each of the dielectric spacers facing the source/drain epitaxial layer is convex toward the source/drain epitaxial layer.
18. The semiconductor device of claim 17 , wherein the dielectric spacers comprise at least one of SiOC, SiOCN and SiCN.
19. The semiconductor device of claim 17 , wherein the source/drain epitaxial layer is made of one or more of Si, SiC, P doped Si, or P doped SiC.
20. The semiconductor device of claim 17 , wherein another end of each of the dielectric spacers facing the gate dielectric layer is concave toward the gate dielectric layer.