Driver circuit
A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.
1. A driver circuit, comprising:
an output circuit including a pull-up transistor; and
a control circuit coupled to the output circuit, the control circuit including a first transistor;
wherein the pull-up transistor is a polysilicon transistor, and the first transistor is an oxide semiconductor transistor;
wherein the control circuit further includes a third transistor having a first end directly connected to a high voltage, a second end directly connected to a second control node, and a third end directly connected to a second clock signal;
wherein the control circuit further includes a fourth transistor having a first end connected to the second control node, a second end connected to a low voltage, and a third end connected to a first control node directly connected to the first transistor;
wherein the control circuit further includes a second transistor having a bottom gate structure, and an auxiliary transistor having a top gate structure; and
wherein the second transistor and the auxiliary transistor commonly share a gate.
2. The driver circuit of claim 1 , wherein the pull-up transistor has a first end connected to a first clock signal, a second end connected to a gate line and one end of a first capacitor, and a third end coupled to the first control node and the other end of the first capacitor, and
wherein the pull-up transistor is a polysilicon transistor.
3. The driver circuit of claim 1 , wherein the first transistor has a first end connected to a high voltage, a second end connected to the first control node, and a third end connected to a previous gate line; and
wherein the first transistor is an oxide semiconductor transistor.
4. The driver circuit of claim 1 , wherein the output circuit further includes the auxiliary transistor having a first end connected to a second end of the pull-up transistor, a second end connected to the low voltage, and a third end coupled to the second control node; and wherein the auxiliary transistor is a polysilicon transistor.
5. The driver circuit of claim 1 , wherein the control circuit further includes the second transistor having a first end connected to the first control node, a second end connected to the low voltage, and a third end connected to the second control node; and wherein the second transistor is an oxide semiconductor transistor.
6. The driver circuit of claim 1 ,
wherein the fourth transistor is an oxide semiconductor transistor.
7. The driver circuit of claim 1 wherein the second transistor and the auxiliary transistor form a stack-up structure.
8. The driver circuit of claim 1 , wherein the second transistor is an oxide semiconductor transistor having a width-to-length ratio WILI, and the auxiliary transistor is a polysilicon semiconductor transistor having a width-to-length ratio WL/LL.
9. The driver circuit of claim 8 , the width-to-length ratio WI/LI of the oxide semiconductor transistor is adjustable without disturbing a circuit layout of the polysilicon transistor.
10. The driver circuit of claim 1 , further comprising a fifth transistor coupled to the first control node, a high voltage, and the first transistor.
11. The driver circuit of claim 10 , wherein the fifth transistor is a polysilicon transistor.
12. The driver circuit of claim 1 , wherein the first transistor is diode-connected.
13. A display device, comprising:
a driver circuit, comprising:
an output circuit including a pull-up transistor; and
a control circuit coupled to the output circuit, the control circuit including a first transistor;
wherein the pull-up transistor is a polysilicon transistor, and the first transistor is an oxide semiconductor transistor;
wherein the control circuit further includes a third transistor having a first end directly connected to a high voltage, a second end directly connected to a second control node, and a third end directly connected to a second clock signal;
wherein the third transistor is an oxide semiconductor transistor;
wherein the control circuit further includes a second transistor having a bottom gate structure, and an auxiliary transistor having a top gate structure, and the second transistor and the auxiliary transistor commonly share a gate.