IC including standard cells and SRAM cells

1. An integrated circuit (IC), comprising:

a plurality of P-type fin field-effect transistors (FinFETs), comprising:

at least one first P-type FinFET comprising a silicon germanium (SiGe) channel region; and

at least one second P-type FinFET comprising a Si channel region,

wherein source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth,

wherein the first depth is greater than the second depth.

2. The IC as claimed in claim 1 , wherein the first depth is from 40 nm to 70 nm, and the second depth is from 35 nm to 65 nm.

3. The IC as claimed in claim 1 , wherein difference in depth between the first depth and the second depth is greater than 3 nm or 5%.

4. The IC as claimed in claim 1 , wherein difference in depth between the first depth and the second depth is from 3 nm to 15 nm or from 5% to 30%.

5. The IC as claimed in claim 1 , further comprising:

at least one standard cell comprising the first P-type FinFET; and

at least one SRAM cell comprising the second P-type FinFET.

6. The IC as claimed in claim 1 , wherein the source/drain regions of the first P-type FinFET and the source/drain regions of the second P-type FinFET comprise boron-doped SiGe.

7. The IC as claimed in claim 6 , wherein Ge atomic concentration in the SiGe channel region of the first P-type FinFET is from 5% to 45% and is less than Ge atomic concentration in the source/drain regions of the first P-type FinFET.

8. The IC as claimed in claim 1 , further comprising:

a plurality of N-type FinFETs,

wherein each of the N-type FinFETs comprises a Si channel region, and source/drain regions of the N-type FinFET comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.

9. An integrated circuit (IC), comprising:

a logic array comprising a plurality of logic cells arranged in rows and columns, wherein each of the logic cells comprises at least one first P-type fin field-effect transistor (FinFET) having a silicon germanium (SiGe) channel region; and

a memory array comprising a plurality of memory cells arranged in rows and columns, wherein each of the memory cells comprises at least one second P-type FinFET having a Si channel region,

wherein the source/drain regions of the first P-type FinFETs and the source/drain regions of the second P-type FinFETs comprise boron-doped SiGe,

wherein source/drain regions of the second P-type FinFET are shallower than source/drain regions of the first P-type FinFET.

10. The IC as claimed in claim 9 , wherein the first P-type FinFETs of the logic cells positioned in the same column of the logic array share a first semiconductor fin, and the first P-type FinFETs of two adjacent logic cells positioned in the same column of the logic array are separated by an isolation P-type FinFET with an underlying active region formed by the first semiconductor fin.

11. The IC as claimed in claim 9 , wherein the first P-type FinFETs of each of the logic cells share a second semiconductor fin, and the second semiconductor fins of two adjacent logic cells positioned in the same column of the logic array are separated by a dielectric-base gate.

12. The IC as claimed in claim 9 , wherein the second P-type FinFETs of the memory cells positioned in the same column of the memory array share a third semiconductor fin, and each of the memory cells comprises an isolation P-type FinFET with an underlying active region formed by the third semiconductor fin.

13. The IC as claimed in claim 9 , wherein the second P-type FinFETs of two adjacent memory cells positioned in the same column of the memory array share a fourth semiconductor fin, and the fourth semiconductor fins of the logic cells positioned in the same column of the logic array are separated by a shallow trench isolation.

14. The IC as claimed in claim 9 , wherein the logic cells are selected from a group consisting of inverter, NAND, NOR, AND, OR, Flip-Flop, SCAN, or a combination thereof.

15. The IC as claimed in claim 9 , wherein the logic array and the memory array each further comprises:

a plurality of N-type FinFETs,

wherein each of the N-type FinFETs comprises a Si channel region, and source/drain regions of the N-type FinFET comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.

16. An integrated circuit (IC), comprising:

a logic array formed by a plurality of logic cells, wherein each of the logic cells comprises a plurality of first P-type fin field-effect transistors (FinFETs); and

a memory array formed by a plurality of memory cells, wherein each of the memory cells comprises a plurality of second P-type FinFETs,

wherein the first P-type FinFETs of each of the logic cells in the logic array share a discontinuous semiconductor fin comprising silicon germanium (SiGe), and the second P-type FinFETs of the memory cells positioned in the same column of the memory array share a continuous semiconductor fin comprising Si,

wherein source/drain regions of the second P-type FinFET are shallower than source/drain regions of the first P-type FinFET.

17. The IC as claimed in claim 16 , wherein the discontinuous semiconductor fins of two adjacent logic cells positioned in the same column of the logic array are separated by a dielectric-base gate.

18. The IC as claimed in claim 16 , wherein Ge atomic concentration in the discontinuous semiconductor fin of the first P-type FinFET is from 5% to 45% and is less than Ge atomic concentration in the source/drain regions of the first P-type FinFET.

19. The IC as claimed in claim 16 , wherein the logic array and the memory array each further comprises:

a plurality of N-type FinFETs,

wherein each of the N-type FinFETs comprises a Si channel region, and source/drain regions of the N-type FinFET comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.

20. The IC as claimed in claim 16 , wherein the logic cells are selected from a group consisting of inverter, NAND, NOR, AND, OR, Flip-Flop, SCAN, or a combination thereof.