IP Library › Granted Patent US 11,056,166
Granted Patent B2
US 11,056,166 · App. 16/514,840 · Granted Jul 6, 2021

Performing a refresh operation based on a characteristic of a memory sub-system

Inventors: Tingjun Xie (Milpitas, CA); Seungjune Jeon (Santa Clara, CA); Zhengang Chen (San Jose, CA); Zhenlei Shen (Milpitas, CA); Charles See Yeung Kwong (Redwood City, CA)
Assignee: Micron Technology, Inc.
G11C11/40607G11C11/1673G11C11/1675G11C11/40626
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Quick Facts
Patent No.
US 11,056,166
App. No.
16/514,840
Granted
Jul 6, 2021
Kind
B2
Abstract

A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.

Claims (46)

1. A method comprising:

performing a refresh operation at a memory sub-system, the refresh operation being performed at a current frequency;

receiving a write count associated with the memory sub-system;

determining, by a processing device, whether the write count associated with the memory sub-system satisfies a write count threshold; and

in response to determining that the write count associated with the memory sub-system satisfies the write count threshold, performing the refresh operation at an increased frequency relative to the current frequency.

2. The method of claim 1 , further comprising:

receiving an operating temperature of the memory sub-system; and

determining whether the operating temperature of the memory sub-system satisfies an operating temperature threshold, wherein the performing of the refresh operation at the increased frequency is further in response to the operating temperature of the memory sub-system satisfying the operating temperature threshold.

3. The method of claim 1 , wherein the refresh operation corresponds to a plurality of write operations to re-write data based on alternating states at one or more units of the memory sub-system.

4. The method of claim 1 , wherein determining whether the write count associated with the memory sub-system satisfies the write count threshold comprises:

determining whether a number of write operations performed at a particular unit of the memory sub-system satisfies a threshold number of write operations, wherein the write count satisfies the write count threshold for the memory sub-system responsive to determining that the number of write operations of the particular unit satisfies the threshold number of write operations.

5. The method of claim 1 , wherein the refresh operation corresponds to a re-writing of data stored at one or more units of the memory sub-system or a reading of the data stored at the one or more units of the memory sub-system.

6. The method of claim 1 , wherein the refresh operation corresponds to a plurality of write operations to re-write data stored at one or more units of the memory sub-system.

7. The method of claim 1 , further comprising:

receiving an operating temperature of the memory sub-system; and

determining whether the operating temperature of the memory sub-system satisfies an operating temperature threshold; and

in response to determining that the operating temperature of the memory sub-system does not satisfy the operating temperature threshold, performing the refresh operation at a lower frequency relative to the increased frequency.

8. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

performing a refresh operation at a memory sub-system, the refresh operation being performed at a current frequency and associated with a change of threshold voltage distributions at the memory sub-system;

receiving a write count associated with the memory sub-system;

determining whether the write count associated with the memory sub-system satisfies a write count threshold; and

in response to determining that the write count associated with the memory sub-system satisfies the write count threshold, performing the refresh operation at an increased frequency relative to the current frequency to change the threshold voltage distributions at the memory sub-system.

9. The non-transitory computer readable medium of claim 8 , the operations further comprising:

receiving an operating temperature of the memory sub-system; and

determining whether the operating temperature of the memory sub-system satisfies an operating temperature threshold, wherein the performing of the refresh operation at the increased frequency is further in response to the operating temperature of the memory sub-system satisfying the operating temperature threshold.

10. The non-transitory computer readable medium of claim 8 , wherein the refresh operation corresponds to a plurality of write operations to re-write data based on alternating states at one or more units of the memory sub-system.

11. The non-transitory computer readable medium of claim 8 , wherein to determine whether the write count associated with the memory sub-system satisfies the write count threshold, the operations further comprise:

determining whether a number of write operations performed at a particular unit of the memory sub-system satisfies a threshold number of write operations, wherein the write count satisfies the write count threshold for the memory sub-system responsive to determining that the number of write operations of the particular unit satisfies the threshold number of write operations.

12. The non-transitory computer readable medium of claim 8 , wherein the refresh operation corresponds to a re-writing of data stored at one or more units of the memory sub-system or a reading of the data stored at the one or more units of the memory sub-system.

13. The non-transitory computer readable medium of claim 8 , wherein the refresh operation corresponds to a plurality of write operations to re-write data stored at one or more units of the memory sub-system.

14. The non-transitory computer readable medium of claim 8 , wherein the refresh operation corresponds to a plurality of write operations to re-write data based on alternating bit values at one or more units of the memory sub-system.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

perform a refresh operation at a memory sub-system, the refresh operation being performed at a current frequency;

receive an error condition associated with the memory sub-system, the error condition corresponding to at least one of a bit error rate or a read-retry trigger rate;

determine whether the error condition associated with the memory sub-system satisfies an error condition threshold; and

in response to determining that the error condition associated with the memory sub-system satisfies the error condition threshold, perform the refresh operation at a different frequency relative to the current frequency.

16. The system of claim 15 , wherein the error condition corresponds to the bit error rate and the error condition threshold corresponds to a bit error rate threshold, and wherein to determine whether the error condition associated with the memory sub-system satisfies the error condition threshold, the processing device is to:

determine whether the bit error rate satisfies the bit error rate threshold.

17. The system of claim 16 , wherein the error condition corresponds to the read-retry trigger rate and the error condition threshold corresponds to a read-retry trigger rate threshold, and wherein to determine whether the error condition associated with the memory sub-system satisfies the error condition threshold, the processing device is to:

determine whether the read-retry trigger rate satisfies the read-retry trigger rate threshold, and wherein the read-retry trigger rate is associated with an error control operation.

18. The system of claim 15 , wherein the refresh operation corresponds to a re-writing of data stored at one or more units of the memory sub-system or a reading of the data stored at the one or more units of the memory sub-system.

19. The system of claim 15 , wherein the refresh operation corresponds to a plurality of write operations to re-write data stored at one or more units of the memory sub-system.

20. The system of claim 15 , wherein the different frequency is higher than the current frequency, and wherein the processing device is further to:

in response to determining that the error condition associated with the memory sub-system does not satisfy the error condition threshold, perform the refresh operation at a decreased frequency relative to the current frequency.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2019
From: XIE, TINGJUN; JEON, SEUNGJUNE; CHEN, ZHENGANG; SHEN, ZHENLEI; KWONG, CHARLES SEE YEUNG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 049783/0184 →
Continuity (1)
Related Publication 20210020229A1 · Jan 21, 2021
Cited By (1)
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