One time programmable memory cell (OTP) including main OTP cell transistor, redundant OTP transistor, and access transistor
A one-time programmable (OTP) memory cell, and an OTP memory and a memory system including the same may be provided. The OTP memory cell includes a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor that are connected in series between a first node in a floating state and a second node. The OTP memory cell is configured to apply a program voltage to gates of the main OTP cell transistor and the redundant OTP cell transistor, and a program access voltage lower than the program voltage to a gate of the access transistor, during a program operation.
1. A one-time programmable (OTP) memory cell comprising:
a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor connected in series between a first node and a second node, the first node being in a floating state,
wherein a program voltage is applied to a first gate of the main OTP cell transistor and a second gate of the redundant OTP cell transistor, a program access voltage is applied to a third gate of the access transistor, the first node is kept in the floating state, and a program allowance voltage is applied to the second node, during a program operation, and
wherein the program access voltage is lower than the program voltage, and the program allowance voltage is lower than the program access voltage.
2. The OTP memory cell of claim 1 , wherein
a read voltage is applied to the first gate of the main OTP cell transistor and the second gate of the redundant OTP cell transistor, a read access voltage is applied to the third gate of the access transistor, the first node is kept in the floating state, and a read allowance voltage is applied to the second node, during a read operation, and
the read voltage is lower than the program voltage, the read access voltage is lower than the program access voltage, and the read allowance voltage is same as the program allowance voltage.
3. The OTP memory cell of claim 2 , wherein:
the read voltage is lower than the program access voltage; and
the read access voltage is lower than the read voltage.
4. The OTP memory cell of claim 1 , wherein:
the program operation includes a first program operation and a second program operation;
program voltage is applied to the first gate of the main OTP cell transistor, the program access voltage is applied to the second gate of the redundant OTP cell transistor and the third gate of the access transistor, and the first node is kept in the floating state, and the program allowance voltage is applied to the second node, in the first program operation; and
the first gate of the main OTP cell transistor is in the floating state, the program voltage is applied to the second gate of the redundant OTP cell transistor, the program access voltage is applied to the third gate of the access transistor, the first node is kept in the floating state, and the program allowance voltage is applied to the second node, in the second program operation that is subsequent to the first program operation.
5. The OTP memory cell of claim 4 , wherein
a read voltage is applied to the first gate of the main OTP cell transistor and the second gate of the redundant OTP cell transistor, a read access voltage is applied to the third gate of the access transistor, the first node is kept in the floating state, and a read allowance voltage is applied to the second node, during a read operation, and
the read voltage is lower than the program voltage, the read access voltage is lower than the program access voltage, and the read allowance voltage is same as the program allowance voltage.
6. The OTP memory cell of claim 5 , wherein:
the read voltage is lower than the program access voltage; and
the read access voltage is lower than the read voltage.
7. A one-time programmable (OTP) memory comprising:
an OTP memory cell array including a plurality of OTP memory cells that are connected between a plurality of first row lines, a plurality of second row lines, a plurality of selection lines, and a plurality of bit lines;
a row decoder configured to decode a row address to generate a plurality of word line selection signals;
a row driver configured to drive the plurality of first row lines, the plurality of second row lines, and the plurality of selection lines in response to the plurality of word line selection signals;
a column decoder configured to decode a column address to generate a plurality of column selection signals; and
an input/output (I/O) gating circuit configured to apply input data to bit lines selected from among the plurality of bit lines in response to the plurality of column selection signals in a program operation,
wherein each of the OTP memory cells comprises a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor that are connected in series between a first node in a floating state and a corresponding bit line from among the plurality of bit lines,
the main OTP cell transistor comprises a first gate connected to a corresponding first row line from among the plurality of first row lines,
the redundant OTP cell transistor comprises a second gate connected to a corresponding second row line from among the plurality of second row lines, and
the access transistor comprises a third gate connected to a corresponding selection line from among the plurality of selection lines, and wherein the row driver is configured to,
select a first row line, a second row line, and a selection line from among the plurality of first row lines, the plurality of second row lines, and the plurality of selection lines, respectively, in response to the plurality of word line selection signals, and
apply a program voltage to the selected first row line and the selected second row line and a program access voltage to the selected selection line in the program operation, the program access voltage being lower than the program voltage during the program operation,
wherein the I/O gating circuit is configured to apply a program allowance voltage in response to the input data to the selected bit lines, during the program operation, and
wherein the first node is kept in the floating state during the program operation, and the program allowance voltage is lower than the program access voltage.
8. The OTP memory of claim 7 , wherein
the row driver is configured to apply a read voltage to the selected first and second row lines and a read access voltage to the selected selection line, during a read operation,
the I/O gating circuit is configured to apply a read allowance voltage to the selected bit lines, during the read operation,
the first node is kept in the floating state during the read operation, the read voltage is lower than the program voltage, and the read access voltage is lower than the program access voltage, and
the read allowance voltage is same as the program allowance voltage.
9. The OTP memory of claim 8 , wherein:
the read voltage is lower than the program access voltage; and
the read access voltage is lower than the read voltage.
10. The OTP memory of claim 7 , wherein:
the program operation includes a first program operation and a second program operation;
the row driver is configured to,
apply the program voltage to the selected first row line and the program access voltage to the selected second row line and the selected selection line, in the first program operation, and
keep the selected first row line be in the floating state, apply the program voltage to the selected second row line, and apply the program access voltage to the selected selection line, in the second program operation that is subsequent to the first program operation;
the I/O gating circuit is configured to apply a program allowance voltage om response to the input data to the selected bit lines, during the first program operation and the second program operation; and
the first node is kept in the floating state during the first program operation and the second program operation.
11. The OTP memory of claim 10 , wherein
the row driver is configured to apply a read voltage to the selected first row line and the selected second row line and a read access voltage to the selected selection line, in a read operation,
the I/O gating circuit is configured to apply a read allowance voltage to the selected bit line during the read operation, and
the first node is kept in the floating state during the read operation, the read voltage is lower than the program voltage, the read access voltage is lower than the program access voltage, and the read allowance voltage is same as the program allowance voltage.
12. The OTP memory of claim 11 , wherein:
the read voltage is lower than the program access voltage; and
the read access voltage is lower than the read voltage.
13. The OTP memory of claim 10 , wherein the I/O gating circuit configured to,
apply the input data to the selected bit lines the first program operation or the second program operation, and
transmit currents flowing through the selected bit lines in a read operation.
14. The OTP memory of claim 13 , wherein
the I/O gating circuit is configured to apply a program prohibition voltage to non-selected bit lines in response to the input data, in the program operation, the first program operation, or the second program operation, and
the program prohibition voltage is higher than the program allowance voltage.
15. A memory system comprising:
a controller configured to transmit a program command or a read command, an address signal, and input data, and receive output data; and
a one-time programmable (OTP) memory configured to receive one of the program command or the read command, the address signal, and the input data, and transmit the output data, the OTP memory including,
an OTP memory cell array including a plurality of OTP memory cells that are connected between a plurality of first row lines, a plurality of second row lines, a plurality of selection lines, and a plurality of bit lines,
a row decoder configured to decode a row address included in the address signal to generate a plurality of word line selection signals, and
a row driver configured to drive the plurality of first row lines, the plurality of second row lines, and the plurality of selection lines in response to the plurality of word line selection signals,
a column decoder configured to decode a column address to generate a plurality of column selection signals; and
an input/output (I/O) gating circuit configured to apply input data to bit lines selected from among the plurality of bit lines in response to the plurality of column selection signals in a program operation,
wherein each of the OTP memory cells comprises,
a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor that are connected in series between a first node in a floating state and a corresponding bit line from among the plurality of bit lines,
the main OTP cell transistor comprises a first gate connected to a corresponding first row line from among the plurality of first row lines,
the redundant OTP cell transistor comprises a second gate connected to a corresponding second row line from among the plurality of second row lines, and
the access transistor comprises a third gate connected to a corresponding selection line from among the plurality of selection lines, and wherein the row driver is configured to,
select a first row line, a second row line, and a selection line from among the plurality of first row lines, the plurality of second row lines, and the plurality of selection lines, respectively, in response to the plurality of word line selection signals, and
apply a program voltage to the selected first row line and the selected second row line, and a program access voltage to the selected selection line in response to the program command, the program access voltage being lower than the program voltage, during the program operation,
wherein the I/O gating circuit is configured to apply a program allowance voltage in response to the input data to the selected bit lines, during the program operation, and
wherein the first node is kept in the floating state during the program operation, and the program allowance voltage is lower than the program access voltage.
16. The memory system of claim 15 , wherein
the row driver is configured to apply a read voltage to the selected first row line and the selected second row line and a read access voltage to the selected selection line, during a read operation,
the I/O gating circuit is configured to apply to a read allowance voltage to the selected bit lines, during the read operation, and
the first node is kept in the floating state during the read operation, the read voltage is lower than the program voltage, the read access voltage is lower than the program access voltage, and the read allowance voltage is same as the program allowance voltage.
17. The memory system of claim 16 , wherein:
the read voltage is lower than the program access voltage; and
the read access voltage is lower than the read voltage.
18. The memory system of claim 15 , wherein:
the program operation includes a first program operation and a second program operation; and
the row driver is configured to,
apply the program voltage to the selected first row line and the program access voltage to the selected second row line and the selected selection line in the first program operation, and
keep the selected first row line to be in the floating state, apply the program voltage to the selected second row line, and apply the program access voltage to the selected selection line in the second program operation that is subsequent to the first program operation,
wherein the I/O gating circuit is configured to apply a program allowance voltage in response to the input data to the selected bit lines, during the first program operation and the second program operation, and
wherein the first node is kept in the floating state during the first program operation and the second program operation.
19. The memory system of claim 18 , wherein,
the row driver is configured to apply a read voltage to the selected first row line and the selected second row line and a read access voltage to the selected selection line in a read operation,
the I/O gating circuit is configured to apply a read allowance voltage to the selected bit line during the read operation, and
the first node is kept in the floating state during the read operation, the read voltage is lower than the program voltage, the read access voltage is lower than the program access voltage, and the read allowance voltage is same as the program allowance voltage.
20. The memory system of claim 19 , wherein:
the read voltage is lower than the program access voltage; and
the read access voltage is lower than the read voltage.