IP Library Granted Patent US 10,714,449
Granted Patent B2
US 10,714,449 · App. 16/515,588 · Granted Jul 14, 2020

Die processing

Inventor: Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Invensas Bonding Technologies, Inc.
H01L24/80H01L21/67046H01L21/67051H01L21/67132H01L21/67253H01L21/6836H01L21/6838H01L21/78H01L23/48H01L24/97H01L25/065H01L25/50H01L21/67144H01L24/81H01L2221/68322H01L2221/68336H01L2221/68363H01L2221/68381H01L2224/80006H01L2224/80011H01L2224/80012H01L2224/80013H01L2224/80019H01L2224/80031H01L2224/80895H01L2224/80896H01L2224/81005H01L2224/81801H01L2224/97
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,714,449
App. No.
16/515,588
Granted
Jul 14, 2020
Kind
B2
Abstract

Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

Claims (39)

1. A method comprising:

applying, to a substrate including a wafer, a protective layer to a bonding surface of the wafer;

singulating the wafer and protective layer into a plurality of semiconductor die components;

removing the protective layer to expose an individual bonding surface on each semiconductor die component of the plurality of semiconductor die components; and

preparing the individual bonding surface of one or more semiconductor die components of the plurality of semiconductor die components for bonding to a surface of another substrate.

2. The method of claim 1 , wherein the protective layer is a first protective layer on a first bonding surface of the wafer and the substrate comprises a second protective layer on a second bonding surface of the wafer, the second surface being different than the first surface and the method further comprising:

removing the second protective layer.

3. The method of claim 1 , wherein preparing the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components comprises plasma-activating the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

4. The method of claim 1 , wherein the substrate is a first substrate and the bonding surface is a first bonding surface, the method further comprising:

bonding the individual bonding surface of at least one semiconductor die component of the plurality of semiconductor die components to a second bonding surface of a second substrate.

5. The method of claim 4 , wherein bonding the individual bonding surface of the at least one semiconductor die component of the plurality of semiconductor die components to the second bonding surface of the second substrate comprises:

directly bonding the individual bonding surface of the at least one semiconductor die component of the plurality of semiconductor die components to the second bonding surface of the second substrate without adhesive or an intervening layer.

6. The method of claim 4 , wherein bonding the individual bonding surface of the one or more of the plurality of semiconductor die components to the second bonding surface of the second substrate comprises:

hybrid-bonding the individual bonding surface of the at least one semiconductor die component of the plurality of semiconductor die components to the second bonding surface of the second substrate.

7. The method of claim 6 , further comprising:

activating the second bonding surface of the second substrate for the hybrid-bonding.

8. The method of claim 1 , further comprising:

cleaning the plurality of semiconductor die components using a megasonic cleaning process.

9. The method of claim 1 , further comprising:

etching an edge of individual semiconductor die components of the plurality of semiconductor die components to remove particles from the edge of the individual semiconductor die components of the plurality of semiconductor die components.

10. The method of claim 9 , further comprising:

applying a protective coating to a substantially planar surface of each semiconductor die component of the plurality of semiconductor die components prior to the etching to protect the substantially planar surface from an etchant.

11. The method of claim 1 , further comprising:

bonding the individual bonding surface of a first semiconductor die component of the plurality of semiconductor die components to the individual bonding surface of a second semiconductor die component of the plurality of semiconductor die components.

12. A method comprising:

singulating a wafer to provide a plurality of semiconductor die components;

removing a protective layer from a bonding surface of one or more semiconductor die components of the plurality of semiconductor die components;

preparing the bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components for bonding to a surface of a substrate; and

direct bonding one or more of the plurality of semiconductor die components to the surface of the substrate.

13. The method of claim 12 , wherein preparing the bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components comprises plasma-activating the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

14. A method comprising:

applying a protective layer or coating to a wafer with a substantially planar surface

singulating the wafer to provide a plurality of semiconductor die components;

removing the protective layer or coating from a bonding surface of one or more semiconductor die components of the plurality of semiconductor die components;

preparing the bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components for bonding to a surface of a substrate; and

hybrid bonding one or more of the plurality of semiconductor die components to the surface of the substrate.

15. The method of claim 14 , wherein preparing the bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components comprises plasma-activating the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

16. The method of claim 14 , further comprising:

cleaning the plurality of semiconductor die components using a megasonic cleaning process.

Assignments (3)
CHANGE OF NAME Recorded Nov 19, 2025
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 073635/0465 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2019
From: UZOH, CYPRIAN EMEKA
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 051055/0585 →
Cited By (5)
US 12,300,661 US 12,406,975 US 12,431,460 US 12,550,799 US 12,604,771