IP Library Granted Patent US 10,868,664
Granted Patent B2
US 10,868,664 · App. 16/515,991 · Granted Dec 15, 2020

Minimizing timestamp error in PTP systems

Inventors: Leonid Goldin (Ottawa, CA); Michael Rupert (Ottawa, CA)
Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
H04L7/08H04L7/0016
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Quick Facts
Patent No.
US 10,868,664
App. No.
16/515,991
Granted
Dec 15, 2020
Kind
B2
Abstract

In accordance with some embodiments of the present invention, a method of minimizing timing error in a precise timing protocol system includes receiving an input 1PPS signal and a clock signal; outputting an output 1PPS signal a number of clock edges after receipt of the input 1PPS signal; adjusting the clock signal until the output 1PPS signal as jumped a clock cycle; and adjusting an offset to bring the output 1PPS signal to within a half clock period. In some embodiments, further adjustments can be made to the timestamp.

Claims (14)

1. A method of minimizing timing error in a precise timing protocol system, comprising:

receiving an input one-pulse-per-second (1PPS) signal and a clock signal;

outputting an output 1PPS signal a number of clock edges after receipt of the input 1PPS signal;

adjusting the clock signal until the output 1PPS signal has jumped a clock cycle; and

adjusting an offset to bring the output 1PPS signal to within a half clock period.

2. A method of setting a time stamp, comprising:

receiving an input one-pulse-per-second (1PPS) signal and an input clock signal;

adjusting the input clock signal to within one half of the input clock signal;

receiving a further correction of an output of the 1PPS signal; and

providing the time stamp that accounts for the one half of the input clock signal adjustment and the further correction.

3. The method of claim 2 , wherein adjusting the input clock signal comprises: receiving the input 1PPS signal and a clock signal;

outputting the output 1PPS signal a number of clock edges after receipt of the input 1PPS signal;

adjusting the clock signal until the output 1PPS signal has jumped a clock cycle; and

adjusting an offset to bring the output 1PPS signal to within a half clock period.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2026
From: RENESAS ELECTRONICS AMERICA INC.
To: SITIME CORPORATION
Reel/Frame 075809/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2019
From: GOLDIN, LEONID; RUPERT, MICHAEL JOHN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 049885/0975 →
Continuity (3)
Provisional Application 62701413 · Jul 20, 2018
Provisional Application 62703286 · Jul 25, 2018
Related Publication 20200028666A1 · Jan 23, 2020
Cited By (2)
US 12,294,967 US 12,608,039