System and method for time synchronization between multiple operating systems

1 . A system for time synchronization between multiple operating systems, the system comprising:

a Field Programmable Gate Array (FPGA) configured to obtain and maintain absolute time;

multiple operating systems configured to obtain the absolute time from the FPGA and perform time synchronization based on the obtained absolute time;

a main board comprising an oscillator and an internal counter, wherein the FPGA configured to maintain the absolute time comprises the FPGA configured to increase the absolute time, by the internal counter, based on the oscillator on the main board; and

one or more daughter boards coupled to the main board, and wherein:

the FPGA is further configured to transmit a one pulse per second (1PPS) signal to the one or more daughter boards, and

the one or more daughter boards are configured to:

receive the 1PPS signal;

detect a digital input (DI) event when the multiple operating systems obtain the absolute time from the FPGA;

generate a timestamp indicative of a time deviation between a rising edge of the 1PPS signal and the detection of the DI event; and

transmit a DI event message and the timestamp to the main board based on detecting the DI event.

2 . The system of claim 1 , further comprising one or more external clock sources.

3 . The system of claim 2 , wherein the FPGA configured to obtain the absolute time comprises the FPGA configured to:

obtain time information from one of the one or more external clock sources and decode the time information to obtain the absolute time; and/or

obtain the absolute time from one of the multiple operating systems.

4 . The system of claim 1 ,

wherein the FPGA and the multiple operating systems are disposed on the main board.

5 . The system of claim 1 , wherein the FPGA is configured to generate the DI event.

6 . The system of claim 5 , wherein the one or more daughter boards detecting the DI event comprises the one or more daughter boards receiving the DI event from the FPGA.

7 . A method for time synchronization between multiple operating systems associated with a system, the method comprising:

obtaining and maintaining absolute time by a Field Programmable Gate Array (FPGA);

obtaining the absolute time from the FPGA and performing time synchronization based on the obtained absolute time by multiple operating systems,

wherein the system comprises the FPGA, the multiple operating systems, a main board and one or more daughter boards coupled to the main board, the main board comprising an oscillator and an internal counter, and maintaining the absolute time by the FPGA comprises increasing the absolute time, by the internal counter, based on the oscillator on the main board, and

the method further comprising:

transmitting a one pulse per second (1PPS) signal by the FPGA to one or more daughter boards, and by the one or more daughter boards:

receiving the 1PPS signal;

detecting a digital input (DI) event when the multiple operating systems obtain the absolute time from the FPGA;

generating a timestamp indicative of a time deviation between a rising edge of the 1PPS and the detecting of the DI event; and

transmitting a DI event message and the timestamp to the main board based on detecting the DI event.

8 . The method of claim 7 , wherein obtaining the absolute time by the FPGA comprises:

obtaining time information from one of one or more external clock sources and decoding the time information to obtain the absolute time; and/or

obtaining the absolute time from one of the multiple operating systems.

9 . The method of claim 7 , wherein the FPGA and the multiple operating systems are disposed on the main board.

10 . The method of claim 7 , further comprising generating the DI event using the FPGA.

11 . The method of claim 10 , wherein the one or more daughter boards detecting the DI event comprises the one or more daughter boards receiving the DI event from the FPGA.

12 . At least one computer-readable storage medium comprising processor executable instructions that, when executed by a Field Programmable Gate Array (FPGA) of a main board, cause the FPGA to:

obtain and maintain absolute time using an oscillator and an internal counter, wherein maintaining the absolute time comprises increasing the absolute time, by the internal counter, based on the oscillator on the main board;

output the absolute time to multiple operating systems to perform time synchronization between the FPGA and the operating systems; and

cause transmission of a one pulse per second (1PPS) signal to one or more daughter boards to cause the one or more daughter boards to:

receive the 1PPS signal;

detect a digital input (DI) event when the multiple operating systems obtain the absolute time from the FPGA;

generate a timestamp indicative of a time deviation between a rising edge of the 1PPS and the detection of the DI event; and

transmit a DI event message and the timestamp to the main board.

13 . The at least one computer-readable storage medium of claim 12 , wherein obtaining the absolute time by the FPGA comprises:

obtaining time information from one of one or more external clock sources and decoding the time information to obtain the absolute time; and/or

obtaining the absolute time from one of the multiple operating systems.

14 . The at least one computer-readable storage medium of claim 12 , wherein the processor executable instructions cause the FPGA to generate the DI event.

15 . The at least one computer-readable storage medium of claim 14 , wherein the one or more daughter boards detecting the DI event comprises the one or more daughter boards receiving the DI event from the FPGA.